Static timing analysis for flexible TFT circuits. - Chao-Hsuan Hsu; Chester Liu; En-Hua Ma; James Chien-Mo Li (DAC, 2010)

Placement Optimization of Flexible TFT Digital Circuits. - Chester Liu; En-Hua Ma; Wen-En Wei; Chien-Mo James Li; I-Chun Cheng; Yung-Hui Yeh (IEEE Des. Test Comput., 2011)

Implementation of a highly scalable blokus duo solver on FPGA. - Chester Liu (FPT, 2013)

A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS. - Phil Knag; Chester Liu; Zhengya Zhang (VLSI Circuits, 2016)

A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. - Chester Liu; Sung-Gun Cho; Zhengya Zhang (A-SSCC, 2017)

Inference and Learning Hardware Architecture for Neuro- Inspired Sparse Coding Algoerithm. - Chester Liu; Zhengya Zhang (BioCAS, 2018)

A 2.56-mm2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS. - Chester Liu; Sung-Gun Cho; Zhengya Zhang (IEEE J. Solid State Circuits, 2018)

SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. - Jie-Fang Zhang; Ching-En Lee; Chester Liu; Yakun Sophia Shao; Stephen W. Keckler; Zhengya Zhang (VLSI Circuits, 2019)

A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification. - Thomas Chen 003; Ching-En Lee; Chester Liu; Zhengya Zhang (IEEE J. Solid State Circuits, 2019)

A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. - Chester Liu; Jacob Botimer; Zhengya Zhang (CICC, 2021)

PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. - Sung-Gun Cho; Wei Tang 010; Chester Liu; Zhengya Zhang (VLSI Circuits, 2021)

SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. - Jie-Fang Zhang; Ching-En Lee; Chester Liu; Yakun Sophia Shao; Stephen W. Keckler; Zhengya Zhang (IEEE J. Solid State Circuits, 2021)

NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. - Teyuh Chou; Wei Tang 010; Mihai D. Rotaru; Chester Liu; Rahul Dutta; Sharon Lim Pei Siang; David Ho Soon Wee; Surya Bhattacharya; Zhengya Zhang (VLSI Technology and Circuits, 2022)

Energy-Efficient Parallel Interconnects for Chiplet Integration. - Wei Tang 010; Chester Liu; Zhengya Zhang (IEEE Micro, 2025)