Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation. - Shagun Bajoria; Vineet Kumar Singh; Raju Kunde; Chetan D. Parikh (ISLPED, 2008)

10 Gbps Current Mode Logic I/O Buffer. - Akhil Rathore; Chetan D. Parikh (VDAT, 2013)

A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier. - Vivek Verma; Chetan D. Parikh (VDAT, 2013)

Novel Analog Calibration Technique for Current-Steering DACs. - Pallavi G. Darji; Chetan D. Parikh (Circuits Syst. Signal Process., 2015)

A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators. - A. Purushothaman; Chetan D. Parikh (Circuits Syst. Signal Process., 2015)

A low power low area capacitor array based Digital to Analog Converter architecture. - A. Purushothaman; Chetan D. Parikh (Microelectron. J., 2015)

New technique to improve transient response of LDO regulators without an off-chip capacitor. - Chetan D. Parikh; Gopal Agarwal (VDAT, 2016)

Novel Analog Calibration Technique for Current-Steering DACs' Dynamic Performance. - Pallavi G. Darji; Chetan D. Parikh (Circuits Syst. Signal Process., 2016)

A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage. - Pallavi G. Darji; Chetan D. Parikh (VDAT, 2017)

A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs. - Uma Mukund Kulkarni; Chetan D. Parikh; Subhajit Sen (VLSID, 2018)

Wake-up circuit for PAM4 receiver. - Vamsi Krishna Guduru; Richa Gupta; Bhavani Lakshmi Polareddy; M. Anish Unnikrishnan; Chetan D. Parikh; Subhajit Sen (ISED, 2019)

High Performance Operational Amplifier with 90dB Gain in SCL 180nm Technology. - Surya Padma; Sounak Das; Subhajit Sen; Chetan D. Parikh (VDAT, 2020)

Digital Calibration of 1.5 bits/stage Algorithmic ADC. - Chinmaye Ramamurthy; Chetan D. Parikh; Subhajit Sen (ISOCC, 2021)

Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration Coefficients. - Chinmaye Ramamurthy; Chetan D. Parikh; Subhajit Sen (VLSID, 2021)

Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches. - Chinmaye Ramamurthy; Chetan D. Parikh; Subhajit Sen (Circuits Syst. Signal Process., 2021)