A Unified Architecture for BCD and Binary Adder/Subtractor. - Chetan Kumar V.; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (DSD, 2011)

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. - Chetan Kumar V.; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISED, 2011)

A Prefix Based Reconfigurable Adder. - Chetan Kumar V.; Sai Phaneendra P.; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISVLSI, 2011)