Chetan Vudadha

According to our database, Chetan Vudadha authored at least 20 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation.

Vikas Shivakumar, Chetan Vudadha

J. Circuits Syst. Comput., January, 2024

2023

Power efficient designs of CNTFET-based ternary SRAM.

Sharvani Gadgil, Goli Naga Sandesh, Chetan Vudadha

Microelectron. J., September, 2023

2022

Optimization of Reversible Circuits Using Gate Pair Classification.

P. Sai Phaneendra, Chetan Vudadha, M. B. Srinivas

SN Comput. Sci., 2022

Design of CNTFET-based Ternary Logic circuits using Low power Encoder.

Siddharth T, Sharvani Gadgil, Chetan Vudadha

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2020

A Novel Low Power Ternary Multiplier Design using CNFETs.

Harita Sirugudi, Sharvani Gadgil, Chetan Vudadha

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design.

P. Veda Bhanu, Chetan Vudadha, Soumya J.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs.

Poojan Patel, Nikita Doddapaneni, Sharvani Gadgil, Chetan Vudadha

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018

Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers.

Chetan Vudadha, Ajay Surya, Saurabh Agrawal, M. B. Srinivas

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Energy efficient design of CNFET-based multi-digit ternary adders.

Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas

Microelectron. J., 2018

Design Methodologies for Ternary Logic Circuits.

Chetan Vudadha, M. B. Srinivas

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017

An ESOP Based Cube Decomposition Technique for Reversible Circuits.

Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas

Proceedings of the Reversible Computation - 9th International Conference, 2017

Optimizing the Reversible Circuits Using Complementary Control Line Transformation.

Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas

Proceedings of the Reversible Computation - 9th International Conference, 2017

2016

An Efficient Design Methodology for CNFET Based Ternary Logic Circuits.

Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

2014

An Optimized Design of Reversible Quantum Comparator.

P. Sai Phaneendra, Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A New Design of an N-Bit Reversible Arithmetic Logic Unit.

Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2012

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.

Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Prefix-Based Optimal Reversible Comparator.

Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.

Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

CNFET based ternary magnitude comparator.

Chetan Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas

Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.

P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas

Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011