Digit systolic algorithms for fine-grain architectures. - Chetana Nagendra; Robert Michael Owens; Mary Jane Irwin (ASAP, 1993)

Edge detection using fine-grained parallelism in VLSI. - Chetana Nagendra; Manjit Borah; Mohan Vishwanath; Robert Michael Owens; Mary Jane Irwin (ICASSP (1), 1993)

Rapid prototyping with programmable control paths. - Raminder Singh Bajwa; Chetana N. Keltcher; Paul Keltcher; Mary Jane Irwin (ASAP, 1994)

The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. - Manjit Borah; Chetana Nagendra; Robert Michael Owens; Mary Jane Irwin (HICSS (1), 1994)

Digit pipelined discrete wavelet transform. - Chetana Nagendra; Mary Jane Irwin; Robert Michael Owens (ICASSP (2), 1994)

Power-delay characteristics of CMOS adders. - Chetana Nagendra; Robert Michael Owens; Mary Jane Irwin (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Unifying carry-sum and signed-digital number representations for low power. - Chetana Nagendra; Robert Michael Owens; Mary Jane Irwin (ISLPD, 1995)

Digit pipelined arithmetic on fine-grain array processors. - Chetana Nagendra; Robert Michael Owens; Mary Jane Irwin (J. VLSI Signal Process., 1995)

Design tradeoffs in CMOS FIR filters. - Chetana Nagendra; Mary Jane Irwin (ICASSP, 1996)

Design tradeoffs in high speed multipliers and FIR filters. - Chetana Nagendra; Robert Michael Owens; Mary Jane Irwin (VLSI Design, 1996)

An optimal time multiplication free algorithm for edge detection on a mesh. - Manjit Borah; Chetana Nagendra; Mohan Vishwanath; Robert Michael Owens; Mary Jane Irwin (J. VLSI Signal Process., 1996)

The AMD Opteron Processor for Multiprocessor Servers. - Chetana N. Keltcher; Kevin J. McGrath; Ardsher Ahmed; Pat Conway (IEEE Micro, 2003)