Design rule optimization of regular layout for leakage reduction in nanoscale design. - Anupama R. Subramaniam; Ritu Singhal; Chi-Chao Wang; Yu Cao (ASP-DAC, 2008)

Pathfinding for 22nm CMOS designs using Predictive Technology Models. - Xia Li; Wei Zhao; Yu Cao 001; Zhi Zhu; Jooyoung Song; David Bang; Chi-Chao Wang; Seung-Hyuk Kang; Joseph Wang; Matt Nowak; Nick Yu (CICC, 2009)

Modeling of layout-dependent stress effect in CMOS design. - Chi-Chao Wang; Wei Zhao; Frank Liu 001; Min Chen 024; Yu Cao 001 (ICCAD, 2009)

The Predictive Technology Model in the Late Silicon Era and Beyond. - Yu Cao 001; Asha Balijepalli; Saurabh Sinha; Chi-Chao Wang; Wenping Wang 004; Wei Zhao (Found. Trends Electron. Des. Autom., 2009)

Simulation of random telegraph Noise with 2-stage equivalent circuit. - Yun Ye; Chi-Chao Wang; Yu Cao 001 (ICCAD, 2010)

Workload-adaptive process tuning strategy for power-efficient multi-core processors. - Jungseob Lee; Chi-Chao Wang; Hamid Reza Ghasemi; Lloyd Bircher; Yu Cao 001; Nam Sung Kim (ISLPED, 2010)

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. - Ritu Singhal; Asha Balijepalli; Anupama R. Subramaniam; Chi-Chao Wang; Frank Liu 001; Sani R. Nassif; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Leakage reduction through optimization of regular layout parameters. - Anupama R. Subramaniam; Ritu Singhal; Chi-Chao Wang; Yu Cao (Microelectron. J., 2012)

The potential of Fe-FET for robust design under variations: A compact modeling study. - Chi-Chao Wang; Yun Ye; Yu Cao 001 (Microelectron. J., 2012)