A routability and performance driven technology mapping algorithm for LUT based FPGA designs. - Chi-Chou Kao; Yen-Tai Lai (ISCAS (1), 1999)

A quadratic programming method for interconnection crosstalk minimization. - Yen-Tai Lai; Chi-Chou Kao; Wu-Chien Shieh (ISCAS (6), 1999)

A technology mapping algorithm for heterogeneous FPGAs. - Chi-Chou Kao; Yen-Tai Lai (ASP-DAC, 2003)

Design of echo cancellation and noise elimination for speech enhancement. - Chi-Chou Kao (IEEE Trans. Consumer Electron., 2003)

Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction. - Chi-Chou Kao; Yen-Tai Lai (ASP-DAC, 2004)

An efficient algorithm for finding the minimal-area FPGA technology mapping. - Chi-Chou Kao; Yen-Tai Lai (ACM Trans. Design Autom. Electr. Syst., 2005)

A High Flexibility Design for Clock Distribution Network in System on Chip. - Chi-Chou Kao (J. Circuits Syst. Comput., 2007)

Computer-aided crosstalk minimisation design for system-on-chip. - Chi-Chou Kao (IET Comput. Digit. Tech., 2008)

A Novel Digital Pixel Sensor System. - Yen-Tai Lai; Chia-Nan Yeh; Chi-Chou Kao (ISCAS, 2009)

An efficient reflection invariance region-based image retrieval framework. - Chi-Chou Kao; Yen-Tai Lai; Chia-Hui Lin (Int. J. Imaging Syst. Technol., 2010)

A Performance-Driven Rotational Invariant Image Retrieval System. - Yen-Tai Lai; Chi-Chou Kao; Tzu-Chiang Tai; Wen-Chun Yeh (J. Inf. Sci. Eng., 2010)

BDD-based synthesis for mixed CMOS/PTL logic. - Chi-Chou Kao (Int. J. Circuit Theory Appl., 2011)

Heuristic Algorithms for Constructing Interference-Free and Delay-Constrained Multicast Trees for Wireless Mesh Networks. - Wen-Lin Yang; Chi-Chou Kao; Cheng-Huang Tung (KSII Trans. Internet Inf. Syst., 2011)

Laplacian-based H.264 intra-prediction mode decision. - Chi-Chou Kao; Yen-Tai Lai; Chao-Feng Tseng (CHINACOM, 2012)

E-Health Design of EEG Signal Classification for Epilepsy Diagnosis. - Chi-Chou Kao (ISBAST, 2013)

Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost Designs. - Chi-Chou Kao; Yen-Tai Lai (J. Circuits Syst. Comput., 2013)

Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable Architectures. - Chi-Chou Kao (IEEE Trans. Parallel Distributed Syst., 2015)

Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction. - Chi-Chou Kao (J. Signal Process. Syst., 2015)

Stereoscopic image generation with depth image based rendering. - Chi-Chou Kao (Multim. Tools Appl., 2017)

Designs of Low Power Snoop for Multiprocessor System on Chip. - Chi-Chou Kao; Yi-Ciang Lin (J. Signal Process. Syst., 2017)

Design and Implementation of Stereoscopic Image Generation. - Chi-Chou Kao (J. Circuits Syst. Comput., 2019)

Resource and Performance Tradeoff for Task Scheduling of Parallel Reconfigurable Architectures. - Chi-Chou Kao (J. Circuits Syst. Comput., 2020)

Performance-driven parallel reconfigurable computing architecture for multi-standard video decoding. - Chi-Chou Kao (Multim. Tools Appl., 2020)

Performance-oriented FPGA-based convolution neural network designs. - Chi-Chou Kao (Multim. Tools Appl., 2023)

Optimizing FPGA-Based Convolutional Neural Network Performance. - Chi-Chou Kao (J. Circuits Syst. Comput., 2023)

Performance-Oriented Layout Synthesis for Quantum Computing. - Chi-Chou Kao; Hung-Yi Lin (Comput. Syst. Sci. Eng., 2024)

Optimizing Layout Synthesis for Quantum Computing Performance. - Chi-Chou Kao; Hung-Yi Lin (J. Circuits Syst. Comput., 2025)