Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. - Chi-Chuan Chuang; Yi-Hsiang Lai; Jie-Hong R. Jiang (DAC, 2014)

A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. - Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang (ICCAD, 2015)

Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. - Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)