A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs. - Chi-Chun Yang; Che-Wei Chou; Jin-Fu Li 001 (Asian Test Symposium, 2013)

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. - Kuan-Te Wu; Jin-Fu Li 001; Yun-Chao Yu; Chih-Sheng Hou; Chi-Chun Yang; Ding-Ming Kwai; Yung-Fa Chou; Chih-Yen Lo (ATS, 2014)

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. - Yun-Chao You; Chi-Chun Yang; Jin-Fu Li 001; Chih-Yen Lo; Chao-Hsun Chen; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (ATS, 2014)

A hybrid built-in self-test scheme for DRAMs. - Chi-Chun Yang; Jin-Fu Li 001; Yun-Chao Yu; Kuan-Te Wu; Chih-Yen Lo; Chao-Hsun Chen; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2015)

DFT Techniques For Efficient 3D IC Interconnect Test For Chiplet and Multi-Die Package. - Anshuman Chandra; Chi-Chun Yang; Quoc Phan; Martin Keim (ETS, 2025)