A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS. - Jafar Savoj; Kenny C.-H. Hsieh; Parag Upadhyaya; Fu-Tai An; Ade Bekele; Stanley Chen; Xuewen Jiang; Kang Wei Lai; Chi Fung Poon; Aman Sewani; Didem Turker; Karthik Venna; et al. (VLSIC, 2012)

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (ISSCC, 2018)

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. - James Hudner; Declan Carey; Ronan Casey; Kay Hearne; Pedro Wilson de Abreu Farias Neto; Ilias Chlis; Marc Erett; Chi Fung Poon; Asma Laraba; Hongtao Zhang 002; Sai Lalith Chaitanya Ambatipudi; David Mahashin; et al. (VLSI Circuits, 2018)

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (IEEE J. Solid State Circuits, 2019)

A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (VLSI Circuits, 2021)

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (IEEE J. Solid State Circuits, 2022)