Advanced Peer Clustering and Firework Query Model in the Peer-to-Peer Network. - Cheuk Hang Ng; Ka Cheung Sia; Chi-Hang Chan (WWW (Posters), 2003)

Bridging the P2P and WWW Divide with DISCOVIR - DIStributed COntent-based Visual Information Retrieval. - Ka Cheung Sia; Cheuk Hang Ng; Chi-Hang Chan (WWW (Posters), 2003)

Using Biased Support Vector Machine to Improve Retrieval Result in Image Retrieval with Self-organizing Map. - Chi-Hang Chan; Irwin King (ICONIP, 2004)

Biased support vector machine for relevance feedback in image retrieval. - Steven Chu-Hong Hoi; Chi-Hang Chan; Kaizhu Huang; Michael R. Lyu; Irwin King (IJCNN, 2004)

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. - Sai-Weng Sin; Li Ding; Yan Zhu 001; He Gong Wei; Chi-Hang Chan; U. Fat Chio; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (ESSCIRC, 2010)

A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2010)

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2010)

A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (A-SSCC, 2011)

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. - Chi-Hang Chan; Yan Zhu 001; U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2011)

A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. - Si-Seng Wong; U. Fat Chio; Chi-Hang Chan; Hou-Lon Choi; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2011)

A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. - U. Fat Chio; Chi-Hang Chan; Hou-Lon Choi; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ESSCIRC, 2011)

A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. - He Gong Wei; Chi-Hang Chan; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (ISSCC, 2011)

A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (VLSIC, 2012)

A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (VLSIC, 2012)

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. - He Gong Wei; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2012)

A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2012)

A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. - Wen-Lan Wu; Yan Zhu 001; Li Ding; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2013)

A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2013)

An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2014)

Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. - Jianwei Liu 005; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2015)

26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISSCC, 2015)

A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages. - Chi-Hang Chan; Yan Zhu 001; Iok-Meng Ho; Wai-Hong Zhang; Chon-Lam Lio; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2016)

A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction. - Jianyu Zhong; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2016)

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS. - Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Si-Seng Wong; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. - Jianwei Liu 005; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. - Wei Wang 177; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2017)

A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC. - Guan-Cheng Wang 002; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2017)

16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. - Chi-Hang Chan; Yan Zhu 001; Iok-Meng Ho; Wai-Hong Zhang; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. - Chi-Hang Chan; Yan Zhu 001; Cheng Li 010; Wai-Hong Zhang; Iok-Meng Ho; Lai Wei; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

Metastablility in SAR ADCs. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Boris Murmann; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC. - Jianyu Zhong; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. - Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. - Arshad Hussain; Sai-Weng Sin; Chi-Hang Chan; Ben Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{ mathrm {cm}}$ -Based Switching. - Dezhi Xing; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Fan Ye 001; Junyan Ren; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H. - Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (A-SSCC, 2018)

A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. - Wenning Jiang; Yan Zhu 001; Chi-Hang Chan; Boris Murmann; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2018)

A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end. - Chi-Hang Chan; Yan Zhu 001; Zi-Hao Zheng; Rui Paulo Martins (ESSCIRC, 2018)

A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ∑Δ ADC Based on the Pipelined-SAR Structure. - Yan Song; Yan Zhu 001; Chi-Hang Chan; Li Geng; Rui Paulo Martins (VLSI Circuits, 2018)

A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. - Chi-Hang Chan; Yan Zhu 001; Wai-Hong Zhang; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS. - Wei Wang 177; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS. - X. Shawn Wang; Xin Jin; Jieqiong Du; Yilei Li; Yuan Du; Chien-Heng Wong; Yen-Cheng Kuan; Chi-Hang Chan; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC. - Guan-Cheng Wang 002; Cheng Li 010; Yan Zhu 001; Jianyu Zhong; Yan Lu 002; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. - Xiaofeng Yang 004; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 0.19 mm2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS. - Yan Zhu 001; Chi-Hang Chan; Zi-Hao Zheng; Cheng Li 010; Jianyu Zhong; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Passive Noise Shaping in SAR ADC With Improved Efficiency. - Yan Song; Chi-Hang Chan; Yan Zhu 001; Li Geng; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area. - Guan-Cheng Wang 002; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Input Correlated Swap-Sampling Technique for Input Driver Power Reduction in a 12b 25MS/s SAR ADC. - Lai Wei; Xiang-Hui Pan; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISCAS, 2019)

A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT. - Xiaofeng Yang 004; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISSCC, 2019)

A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier. - Wenning Jiang; Yan Zhu 001; Minglei Zhang; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2019)

A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ. - Wei Wang 177; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISSCC, 2019)

A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques. - Minglei Zhang; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISSCC, 2019)

A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques. - Minglei Zhang; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 4-b 7-µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation. - Xuewei Lei; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC. - Cheng Li 010; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Background Offset Calibration for Comparator Based on Temperature Drift Profile. - Xiaochao Li; Chi-Hang Chan; Qi Zhang 031; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique. - Dezhi Xing; Yan Zhu 001; Chi-Hang Chan; Franco Maloberti; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. - Jianwei Liu 005; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration. - Yan Song; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2020)

16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input. - Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2020)

16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. - Zihao Zheng; Lai Wei; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (ISSCC, 2020)

A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp. - Kai Xing; Wei Wang 177; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (VLSI Circuits, 2020)

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier. - Wenning Jiang; Yan Zhu 001; Minglei Zhang; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC. - Yan Song; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization. - Wei Wang 177; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps. - Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration. - Jiahao Liu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT. - Xiaofeng Yang 004; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator. - Yanbo Zhang; Shubin Liu; Binbin Tian; Yan Zhu 001; Chi-Hang Chan; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS. - Jin Zhang 034; Xiaoqian Ren; Shubin Liu; Chi-Hang Chan; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER-6. - Jiahao Liu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (A-SSCC, 2021)

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture. - Yanbo Zhang; Jin Zhang 034; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2021)

27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration. - Hongshuai Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2021)

An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC. - Lai Wei; Zihao Zheng; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (VLSI Circuits, 2021)

A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration. - Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (VLSI Circuits, 2021)

Bird's-eye view of analog and mixed-signal chips for the 21st century. - Rui Paulo Martins; Pui-In Mak; Chi-Hang Chan; Jun Yin 001; Yan Zhu 001; Yong Chen 005; Yan Lu 002; Man-Kay Law; Sai-Weng Sin (Int. J. Circuit Theory Appl., 2021)

A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC. - Yan Song; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2021)

A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler. - Wenning Jiang; Yan Zhu 001; Chi-Hang Chan; Boris Murmann; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

LSB-Reused Protection Technique in Secure SAR ADC against Power Side-Channel Attack. - Lele Fang; Jiahao Liu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (AsianHOST, 2022)

An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC. - Yi Zeng; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISCAS, 2022)

A low dropout regulator with PSR under -48dB up to 20GHz for a SARADC reference buffer. - Yi Zeng; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (MWSCAS, 2022)

An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration. - Hongshuai Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations. - Yanbo Zhang; Jin Zhang 034; Shubin Liu; Ruixue Ding; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. - Zihao Zheng; Lai Wei; Jorge Lagos 001; Ewout Martens; Yan Zhu 001; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference. - Yu Duan; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Entropy-Source-Preselection-Based Strong PUF With Strong Resilience to Machine Learning Attacks and High Energy Efficiency. - Jiahao Liu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks and Ultra-Low BER. - Jiahao Liu; Yuanzhe Zhao; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp. - Kai Xing; Wei Wang 177; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT. - Xiang-Hui Pan; Buhui Rui; Yuefeng Cao; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2023)

An ELDC-Free 2.78mW 20MHz-BW 75.5dB-SNDR 4th- Order CTSDM Facilitated by 2nd-Order CT NS-SAR and AC-Coupled Negative-R. - ZiXuan Xu; Kai Xing; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2023)

A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation. - Yuanzhe Zhao; Minglei Zhang; Pengyu He; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2023)

A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness. - Junyan Hao; Minglei Zhang; Yanbo Zhang; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping. - Yanbo Zhang; Junyan Hao; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-Prediction-Unrolled Scheme. - Hongshuai Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input. - Hongzhi Zhao; Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors. - Minglei Zhang; Yuefeng Cao; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (VLSI Technology and Circuits, 2023)

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. - Wenning Jiang; Yan Zhu 001; Chixiao Chen; Hao Xu 005; Qi Liu 010; Ming Liu 022; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling. - Junlin Zhong; Xiaofeng Yang 004; Rui Paulo Martins; Yan Zhu 001; Chi-Hang Chan (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator. - Hongshuai Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC. - Hongzhi Zhao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. - Lai Wei; Zihao Zheng; Nereo Markulic; Jorge Lagos 001; Ewout Martens; Rui Paulo Martins; Yan Zhu 001; Jan Craninckx; Chi-Hang Chan (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 320MHz BW NS TD-ADC Assisted C/DT Hybrid Pipelined ADC with SAB-based Residue Amplifying Filter. - Kai Xing; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (A-SSCC, 2024)

A Compact Low-power 16b SAR ADC using Reservoir-Charge-Redistributed DAC and Configurable Floating-Inverter-Based Comparator. - Chenxi Yuan; Xianghui Pan; Zihao Zheng; Yan Song; R. P. Martins; Yan Zhu 001; Chi-Hang Chan (A-SSCC, 2024)

The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs. - Chi-Hang Chan; Minglei Zhang; Yuefeng Cao; Honazhi Zhao; Rui Paulo Martins; Yan Zhu 001 (CICC, 2024)

A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC. - Pengyu He; Yuanzhe Zhao; Heng Xie; Yang Wang 089; Shouyi Yin; Li Li 064; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (CICC, 2024)

A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew Calibration. - Wei Zhang; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (CICC, 2024)

22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2024)

6.8 A 256×192-Pixel 30fps Automotive Direct Time-of-Flight LiDAR Using 8× Current-Integrating-Based TIA, Hybrid Pulse Position/Width Converter, and Intensity/CNN-Guided 3D Inpainting. - Chaorui Zou; Yaozhong Ou; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (ISSCC, 2024)

An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R. - ZiXuan Xu; Kai Xing; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2024)

A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing. - Yaozhong Ou; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro. - Yuzhao Fu; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Minglei Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 256 × 192 -Pixel Direct Time-of-Flight LiDAR Receiver With a Current-Integrating-Based AFE Supporting 240-m-Range Imaging. - Chaorui Zou; Yaozhong Ou; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (IEEE J. Solid State Circuits, 2024)

CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization. - Yuzhao Fu; Jixuan Li; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2024)

A 48x OSR 105.4-dB SNDR 24-kHz BW CT Zoom ADC with Reset Tri-level DWA and On-chip Negative-R Calibration. - Yuyu Lin; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (CICC, 2025)

A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager. - Yuanzhe Zhao; Yang Wang 089; Yuheng Wang; Heng Xie; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Shouyi Yin; Minglei Zhang (CICC, 2025)

A Reconfigurable 0.69-1.02nJ/Classification Biomedical AI Processor for Intelligent Health Monitoring Devices. - Yuanzhe Zhao; Yuheng Wang; Zijian Wang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (CICC, 2025)

A One-Shot Floating-Point Compute-in-Memory Macro Featuring PVT Robustness and Mismatch Tolerance for Edge LLMs. - Yuanzhe Zhao; Heng Xie; Zijian Wang; Chunlin Tian; Li Li 064; Yan Zhu 001; R. P. Martins; Chi-Hang Chan; Minglei Zhang (CICC, 2025)

A PVT-Robust 5.5GHz Fractional-N Cascaded RO-Based Digital PLL with Voltage-Domain Feedforward Noise Cancellation. - Yu Duan; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input. - Zijian Liu; Minglei Zhang; Wei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

24.5 A 72GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Inputs in 16nm FinFET. - Yannan Zhang; Minglei Zhang; Zehang Wu; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

24.3: A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz ERBW. - Junlin Zhong; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2025)

An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme. - Junyan Hao; Minglei Zhang; Zijian Liu; Yanbo Zhang; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2025)