A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology. - Chi-Hao Hong; Yi-Wei Chiu; Jun-Kai Zhao; Shyh-Jye Jou; Wen-Tai Wang; Reed Lee (SoCC, 2014)

A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. - Chi-Hao Hong; Yi-Wei Chiu; Jun-Kai Zhao; Shyh-Jye Jou; Wen-Tai Wang; Reed Lee (ISCAS, 2015)

Robustness Enhancement of a Class-C Quadrature Oscillator Using Capacitive Source Degeneration Coupling. - Chi-Hao Hong; Chuan-Yi Wu; Yu-Te Liao (IEEE Trans. Circuits Syst. II Express Briefs, 2015)