A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. - Yi-Min Lin; Chi-Heng Yang; Chih-Hsiang Hsu; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A fully parallel BCH codec with double error correcting capability for NOR flash applications. - Chia-Ching Chu; Yi-Min Lin; Chi-Heng Yang; Hsie-Chia Chang (ICASSP, 2012)

A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. - Yi-Hsun Chen; Chi-Heng Yang; Hsie-Chia Chang (VLSI-DAT, 2012)

An area-efficient BCH codec with echelon scheduling for NAND flash applications. - Chi-Heng Yang; Yi-Hsun Chen; Hsie-Chia Chang (ICC, 2013)

An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. - Chi-Heng Yang; Yi-Min Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2015)

3X endurance enhancement by advanced signal processor for 3D NAND flash memory. - Wei Lin; Yu-Cheng Hsu; Tsai-Hao Kuo; Yu-Siang Yang; Szu-Wei Chen; Chun-Wei Tsao; An-Chang Liu; Lih-Yuarn Ou; Tien-Ching Wang; Shao-Wei Yen; Yu-Hsiang Lin; Kuo-Hsin Lai; et al. (ITW, 2017)

Human vs machine: Do customer service chatbots perform better? - Chi-Heng Yang; Ju-Chun Yen; Tawei David Wang (PACIS, 2022)

Large Language Models for Conducting Advanced Text Analytics Information Systems Research. - Benjamin Ampel; Chi-Heng Yang; James Hu 001; Hsinchun Chen (ACM Trans. Manag. Inf. Syst., 2025)