Compensator-Free Mixed-Ripple Adaptive On-Time Controlled Boost Converter. - Chi-Hsiang Huang 001; Hung-Hsien Wu; Chia-Ling Wei (IEEE J. Solid State Circuits, 2018)

Bidirectional Single-Inductor Dual-Supply Converter With Automatic State-Transition for IoT Applications. - Hung-Hsien Wu; Chi-Hsiang Huang 001; Chia-Ling Wei; Jih-Sheng Lai 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. - Xun Sun; Akshat Boora; Rajesh Pamula 001; Chi-Hsiang Huang 001; Diego Peña-Colaiocco; Visvesh S. Sathe 001 (VLSI Circuits, 2020)

UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. - Xun Sun; Akshat Boora; Rajesh Pamula 001; Chi-Hsiang Huang 001; Diego Peña-Colaiocco; Visvesh S. Sathe 001 (VLSI Circuits, 2020)

A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. - Chi-Hsiang Huang 001; Xun Sun; Yidong Chen 005; Rajesh Pamula 001; Arindam Mandal; Visvesh Sathe 001 (ISSCC, 2021)

Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains. - Chi-Hsiang Huang 001; Arindam Mandal; Diego Peña-Colaiocco; Edevaldo Pereira Da Silva; Visvesh S. Sathe 001 (ISSCC, 2022)

An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. - Diego Peña-Colaiocco; Chi-Hsiang Huang 001; Kun-Da Chu; Jacques Christophe Rudell; Visvesh S. Sathe 001 (ISSCC, 2022)

Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. - Chi-Hsiang Huang 001; Yidong Chen 005; Xun Sun; Arindam Mandal; Venkata Rajesh Pamula 001; Nasser A. Kurd; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2022)

Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains. - Chi-Hsiang Huang 001; Arindam Mandal; Diego Peña-Colaiocco; Edevaldo Pereira Da Silva; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2023)

A 32-Channel 85.4dB SNDR Time-multiplexed Neural Recording Frontend Achieving Within-Conversion Artifact Recovery. - Arindam Mandal; Chi-Hsiang Huang 001; Julian Arenas; Wei-En Lee; Philip Anschutz; Amanda L. Jacob; Keshav Ramachandra; Samuel J. Sober; Muhannad S. Bakir; Shaolan Li; Visvesh S. Sathe 001 (CICC, 2025)