On the interval completion of chordal graphs. - Sheng-Lung Peng; Chi-Kang Chen (Discret. Appl. Math., 2006)

A basic-block power annotation approach for fast and accurate embedded software power estimation. - Chien-Min Lee; Chi-Kang Chen; Ren-Song Tsay (VLSI-SoC, 2013)

AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis. - Zih-Ci Huang; Chi-Kang Chen; Ren-Song Tsay (ASP-DAC, 2015)

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. - Pei-Wen Luo; Chi-Kang Chen; Yu-Hui Sung; Wei Wu 024; Hsiu-Chuan Shih; Chia-Hsin Lee; Kuo-Hua Lee; Ming-Wei Li; Mei-Chiang Lung; Chun-Nan Lu; Yung-Fa Chou; Po-Lin Shih; et al. (VLSIC, 2015)

An accurate and flexible early memory system power evaluation approach using a microcomponent method. - Chi-Kang Chen; Hsin-I Wu; Chi-Ting Hsiao; Ren-Song Tsay (CODES+ISSS, 2016)

Poster Paper: An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. - Hsuan-Man Chen; Chi-Kang Chen; Hsin-I Wu; Ren-Song Tsay (ICHI, 2016)

An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. - Hsuan-Man Chen; Chi-Kang Chen; Hsin-I Wu; Ren-Song Tsay (ICHI, 2016)

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. - Tah-Kang Joseph Ting; Gyh-Bin Wang; Ming-Hung Wang; Chun-Peng Wu; Chun-Kai Wang; Chun-Wei Lo; Li-Chin Tien; Der-Min Yuan; Yung-Ching Hsieh; Jenn-Shiang Lai; Wen-Pin Hsu; Chien-Chih Huang; et al. (ISSCC, 2017)

A highly efficient full-system virtual prototype based on virtualization-assisted approach. - Hsin-I Wu; Chi-Kang Chen; Tsung-Ying Lu; Ren-Song Tsay (DATE, 2018)

Trojan Horse Detection for RISC-V Cores Using Cross-Auditing. - Wei-Po Huang; Shi-Yu Huang; Chi-Kang Chen; Siang-Cheng Huang (ATS, 2024)

A Scalable Authentication Scheme for Detecting Unauthorized Dice in A Multi-Die IC. - Zheng-Hao Wang; Shi-Yu Huang; Chi-Kang Chen (SMACD, 2025)