A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology. - Ching-Che Chung; Chi-Kuang Lo (IEICE Electron. Express, 2016)

A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling. - Ching-Che Chung; Wei-Siang Su; Chi-Kuang Lo (IEEE Trans. Very Large Scale Integr. Syst., 2016)