A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. - Hao-I Yang; Shih-Chi Yang; Mao-Chih Hsia; Yung-Wei Lin; Yi-Wei Lin; Chien-Hen Chen; Chi-Shin Chang; Geng-Cing Lin; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; et al. (SoCC, 2011)

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. - Hao-I Yang; Yi-Wei Lin; Mao-Chih Hsia; Geng-Cing Lin; Chi-Shin Chang; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan-Chun Lien; Hung-Yu Li; Kuen-Di Lee; et al. (ISCAS, 2012)

A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. - Yi-Wei Lin; Hao-I Yang; Geng-Cing Lin; Chi-Shin Chang; Ching-Te Chuang; Wei Hwang; Chia-Cheng Chen; Willis Shih; Huan-Shun Huang (ISLPED, 2012)

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. - Chi-Shin Chang; Hao-I Yang; Wei-Nan Liao; Yi-Wei Lin; Nan-Chun Lien; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming-Hsien Tu; Huan-Shun Huang; Yong-Jyun Hu; et al. (ISCAS, 2013)

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. - Wei-Nan Liao; Nan-Chun Lien; Chi-Shin Chang; Li-Wei Chu; Hao-I Yang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Ming-Hsien Tu; Huan-Shun Huang; Jian-Hao Wang; Paul-Sen Kan; et al. (SoCC, 2013)