Concurrent Test Generation Using AI Techniques. - Chi W. Yau (ITC, 1986)

Trouble-Shooting: A Key to Process Improvement. - Chi W. Yau; Song-Lin Chang; Bruce F. Jordan; Joe J. Schwermann; Joan A. Wellman (ITC, 1988)

An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test Access Port Controller. - Anton T. Dahbura; M. Ümit Uyar; Chi W. Yau (ITC, 1989)

A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects. - Najmi T. Jarwala; Chi W. Yau (ITC, 1989)

A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects. - Najmi T. Jarwala; Chi W. Yau (ITC, 1989)

The boundary-scan master: target applications and functional requirements. - Chi W. Yau; Najmi T. Jarwala (ITC, 1990)

Achieving Board-Level BIST Using the Boundary-Scan Master. - Najmi T. Jarwala; Chi W. Yau (ITC, 1991)

A Framework for Boundary-Scan Based System Test Diagnosis. - Najmi T. Jarwala; Paul Stiling; Enn Tammaru; Chi W. Yau (ITC, 1992)

A structured approach to board-level BIST using the boundary-scan master. - Najmi T. Jarwala; Chi W. Yau (Microprocess. Microsystems, 1993)

Lessons Learned from Practical Applications of BIST/B-S Technology. - Najmi T. Jarwala; Paul W. Rutkowski; Shianling Wu; Chi W. Yau (Asian Test Symposium, 1996)