Low Power Multiplier with Bypassing and Tree Strucuture. - Ko-Chi Kuo; Chi-Wen Chou (APCCAS, 2006)

A Low-Power Multiplier with Bypassing Logic and Operand Decomposition. - Ko-Chi Kuo; Chi-Wen Chou (IMECS, 2006)

Low power and high speed multiplier design with row bypassing and parallel architecture. - Ko-Chi Kuo; Chi-Wen Chou (Microelectron. J., 2010)