An optimal transistor-chaining algorithm for CMOS cell layout. - Chi-Yi Hwang; Yung-Ching Hsieh; Youn-Long Lin; Yu-Chin Hsu (ICCAD, 1989)

LiB: A Cell Layout Generator. - Yung-Ching Hsieh; Chi-Yi Hwang; Youn-Long Lin; Yu-Chin Hsu (DAC, 1990)

A fast transistor-chaining algorithm for CMOS cell layout. - Chi-Yi Hwang; Yung-Chin Hsieh; Youn-Long Lin; Yu-Chin Hsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. - Chi-Yi Hwang; Yung-Ching Hsieh; Youn-Long Lin; Yu-Chin Hsu (DAC, 1991)

LiB: a CMOS cell compiler. - Yung-Ching Hsieh; Chi-Yi Hwang; Youn-Long Lin; Yu-Chin Hsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Channel density reduction by routing over the cells. - Min-Siang Lin; Hourng-Wern Perng; Chi-Yi Hwang; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. - Chi-Yi Hwang; Yung-Ching Hsieh; Youn-Long Lin; Yu-Chin Hsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

A Hierarchical Test Scheme for System-On-Chip Designs. - Jin-Fu Li 001; Hsin-Jung Huang; Jeng-Bin Chen; Chih-Pin Su; Cheng-Wen Wu; Chuang Cheng; Shao-I Chen; Chi-Yi Hwang; Hsiao-Ping Lin (DATE, 2002)

A Hierarchical Test Methodology for Systems on Chip. - Jin-Fu Li 001; Hsin-Jung Huang; Jeng-Bin Chen; Chih-Pin Su; Cheng-Wen Wu; Chuang Cheng; Shao-I Chen; Chi-Yi Hwang; Hsiao-Ping Lin (IEEE Micro, 2002)