Application-Driven Design Automation for Microprocessor Design. - Iksoo Pyo; Ching-Long Su; Ing-Jer Huang; Kuo-Rueih Pan; Yong-Seon Koh; Chi-Ying Tsui; Hsu-Tsun Chen; Gino Cheng; Shihming Liu; Shiqun Wu; Alvin M. Despain (DAC, 1992)

Technology Decomposition and Mapping Targeting Low Power Dissipation. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (DAC, 1993)

Efficient estimation of dynamic power consumption under a real delay model. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (ICCAD, 1993)

Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. - Ching-Long Su; Chi-Ying Tsui; Alvin M. Despain (COMPCON, 1994)

Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (DAC, 1994)

Low power state assignment targeting two-and multi-level logic implementations. - Chi-Ying Tsui; Massoud Pedram; Chih-Ang Chen; Alvin M. Despain (ICCAD, 1994)

Saving Power in the Control Path of Embedded Processors. - Ching-Long Su; Chi-Ying Tsui; Alvin M. Despain (IEEE Des. Test Comput., 1994)

Power efficient technology decomposition and mapping under an extended power consumption model. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Power estimation methods for sequential logic circuits. - Chi-Ying Tsui; José Monteiro 001; Massoud Pedram; Srinivas Devadas; Alvin M. Despain; Bill Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Improving the Efficiency of Power Simulators by Input Vector Compaction. - Chi-Ying Tsui; Radu Marculescu; Diana Marculescu; Massoud Pedram (DAC, 1996)

Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. - Chi-Ying Tsui; José Monteiro 001; Massoud Pedram; Srinivas Devadas; Alvin M. Despain; Bill Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 1996)

A Power Estimation Framework for Designing Low Power Portable Video Applications. - Chi-Ying Tsui; Kai-Keung Chan; Qing Wu 002; Chih-Shun Ding; Massoud Pedram (DAC, 1997)

An efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms. - Xiao-Dong Zhang 001; Chi-Ying Tsui (ICASSP, 1997)

Low power motion estimation design using adaptive pixel truncation. - Zhong-Li He; Kai-Keung Chan; Chi-Ying Tsui; Ming L. Liou (ISLPED, 1997)

Towards the capability of providing power-area-delay trade-off at the register transfer level. - Chun-hong Chen; Chi-Ying Tsui (ISLPED, 1998)

Generic VLSI architecture for block-matching motion estimation algorithms. - Zhong-Li He; Ming L. Liou; Philip C. H. Chan; Chi-Ying Tsui (Int. J. Imaging Syst. Technol., 1998)

Accurate and efficient power simulation strategy by compacting the input vector set. - Chi-Ying Tsui; Massoud Pedram (Integr., 1998)

Gate-level power estimation using tagged probabilistic simulation. - Chih-Shun Ding; Chi-Ying Tsui; Massoud Pedram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Low-power state assignment targeting two- and multilevel logic implementations. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Timing Optimization of Logic Network Using Gate Duplication. - Chun-hong Chen; Chi-Ying Tsui (ASP-DAC, 1999)

An Integrated Battery-Hardware Model for Portable Electronics. - Massoud Pedram; Chi-Ying Tsui; Qing Wu 002 (ASP-DAC, 1999)

Finite state machine partitioning for low power. - Wai-Kwong Lee; Chi-Ying Tsui (ISCAS (1), 1999)

Low power ACS unit design for the Viterbi decoder [CDMA wireless systems]. - Chi-Ying Tsui; Roger Shu-Kwan Cheng; Curtis Ling (ISCAS (1), 1999)

Unequal error protection for wireless transmission of MPEG audio. - Chi Wai Yung; Hung Fai Fu; Chi-Ying Tsui; Roger S. Cheng; D. George (ISCAS (6), 1999)

Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage. - Oliver Yuk-Hang Leung; Chung-Wai Yue; Chi-Ying Tsui; Roger S. Cheng (ISLPED, 1999)

Adaptive tracking of optimal bit and power allocation for OFDM systems in time-varying channels. - Sai Kit Lai; Roger S. Cheng; Khaled Ben Letaief; Chi-Ying Tsui (WCNC, 1999)

A/I Net: a network that integrates ATM and IP. - Chin-Tau Lea; Chi-Ying Tsui; Bo Li 001; C.-Y. Kwan; Stanley K.-M. Chan; Angus H.-W. Chan (IEEE Netw., 1999)

VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA. - Oliver Yuk-Hang Leung; Chi-Ying Tsui; Roger S. Cheng (ASP-DAC, 2000)

VLSI implementation of a switch fabric for mixed ATM and IP traffic. - Chi-Ying Tsui; Louis Chung-Yin Kwan; Chin-Tau Lea (ASP-DAC, 2000)

Composite interference cancellation scheme for CDMA systems. - Billy Chi-Kin Poon; Chi-Ying Tsui; Roger S. Cheng (GLOBECOM, 2000)

A reduced complexity implementation of the Log-Map algorithm for turbo-codes decoding. - Yan Wang; Chi-Ying Tsui; Roger Shu-Kwan Cheng (ICASSP, 2000)

A low power VLSI architecture of SOVA-based turbo-code decoder using scarce state transition scheme. - Yan Wang; Chi-Ying Tsui; Roger S. Cheng (ISCAS, 2000)

Low complexity VLSI implementation of a joint successive interference cancellation with interleaving scheme. - Bob Ka-Man Wong; Chi-Ying Tsui; Roger S.-K. Cheng (ISCAS, 2000)

A low complexity architecture of the V-BLAST system. - Wong Kwan Wai; Chi-Ying Tsui; Roger S. Cheng (WCNC, 2000)

Low-power VLSI design for motion estimation using adaptive pixel truncation. - Zhong-Li He; Chi-Ying Tsui; Kai-Keung Chan; Ming L. Liou (IEEE Trans. Circuits Syst. Video Technol., 2000)

Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications. - Chi-Ying Tsui; Roger S.-K. Cheng; Curtis Ling (Wirel. Pers. Commun., 2000)

A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling. - Dongsheng Ma; Wing-Hung Ki; Chi-Ying Tsui; Philip K. T. Mok (ASP-DAC, 2001)

Single-inductor multiple-output switching converters with bipolar outputs. - Dongsheng Ma; Wing-Hung Ki; Philip K. T. Mok; Chi-Ying Tsui (ISCAS (3), 2001)

Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage. - Oliver Yuk-Hang Leung; Chi-Ying Tsui; Roger S.-K. Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches. - Jing Liu; Chun Kit Hung; Mounir Hamdi; Chi-Ying Tsui (Hot Interconnects, 2002)

Low complexity OFDM receiver using Log-FFT for coded OFDM system. - Yan Wang; Hing Mo Lam; Chi-Ying Tsui; Roger S. Cheng; Wai Ho Mow (ISCAS (3), 2002)

A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels. - Kwan-wai Wong; Chi-Ying Tsui; Roger S.-K. Cheng; Wai Ho Mow (ISCAS (3), 2002)

Performance study of OFDM receiver using FFT based on log number system. - Yan Wang; Chi-Ying Tsui; Roger S. Cheng; Wai Ho Mow (VTC Spring, 2002)

Design and implementation of high-speed arbiter for large scale VOQ crossbar switches. - Chun Kit Hung; Mounir Hamdi; Chi-Ying Tsui (ISCAS (2), 2003)

Single-inductor dual-input dual-output switching converter for integrated battery charging and power regulation. - Yat-Hei Lam; Wing-Hung Ki; Chi-Ying Tsui; Philip K. T. Mok (ISCAS (3), 2003)

High performance and low power completion detection circuit. - Hing-mo Lam; Chi-Ying Tsui (ISCAS (5), 2003)

Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming. - Lap-Fai Leung; Chi-Ying Tsui; Wing-Hung Ki (ISCAS (5), 2003)

A pseudo-CCM/DCM SIMO switching converter with freewheel switching. - Dongsheng Ma; Wing-Hung Ki; Chi-Ying Tsui (IEEE J. Solid State Circuits, 2003)

Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode. - Dongsheng Ma; Wing-Hung Ki; Chi-Ying Tsui; Philip K. T. Mok (IEEE J. Solid State Circuits, 2003)

A dual-band switching digital controller for a buck converter. - Martin Yeung-Kei Chui; Wing-Hung Ki; Chi-Ying Tsui (ASP-DAC, 2004)

Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment. - Lap-Fai Leung; Chi-Ying Tsui; Wing-Hung Ki (ASP-DAC, 2004)

Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data. - Lap-Fai Leung; Chi-Ying Tsui; Wing-Hung Ki (ASP-DAC, 2004)

Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process. - Dongsheng Ma; Wing-Hung Ki; Chi-Ying Tsui (ASP-DAC, 2004)

Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity. - Yan Wang; Chi-Ying Tsui; Roger S. Cheng; Wai Ho Mow (ASP-DAC, 2004)

Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus. - Siu-Kei Wong; Chi-Ying Tsui (DATE, 2004)

Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia communication. - Feng Liu; Chi-Ying Tsui (ESTIMedia, 2004)

Least leakage vector assisted technology mapping for total power optimization. - Robert Yi-Ching Au; Chi-Ying Tsui (ISCAS (5), 2004)

Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus. - Siu-Kei Wong; Chi-Ying Tsui (ISCAS (2), 2004)

Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling. - Lap-Fai Leung; Chi-Ying Tsui; Xiaobo Sharon Hu (PATMOS, 2004)

An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction. - Dongsheng Ma; Wing-Hung Ki; Chi-Ying Tsui (IEEE J. Solid State Circuits, 2004)

Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling. - Lap-Fai Leung; Chi-Ying Tsui; Xiaobo Sharon Hu (DATE, 2005)

A Data Discarding Framework for Reducing the Energy Consumption of Viterbi Decoder in Decoding Broadcasted Wireless Multi-Resolution JPEG2000 Images. - Feng Liu; Chi-Ying Tsui (ESTIMedia, 2005)

A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems. - Jin Jie; Chi-Ying Tsui; Wai Ho Mow (ISCAS (4), 2005)

Charge redistribution loss consideration in optimal charge pump design. - Wing-Hung Ki; Feng Su; Chi-Ying Tsui (ISCAS (2), 2005)

Gate control strategies for high efficiency charge pumps. - Feng Su; Wing-Hung Ki; Chi-Ying Tsui (ISCAS (2), 2005)

A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation. - Martin Yeung-Kei Chui; Wing-Hung Ki; Chi-Ying Tsui (IEEE J. Solid State Circuits, 2005)

Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors. - Yat-Hei Lam; Suet-Chui Koon; Wing-Hung Ki; Chi-Ying Tsui (ASP-DAC, 2006)

Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback. - Yat-Hei Lam; Wing-Hung Ki; Chi-Ying Tsui (ASP-DAC, 2006)

Ultra-low voltage power management circuit and computation methodology for energy harvesting applications. - Chi-Ying Tsui; Hui Shao; Wing-Hung Ki; Feng Su (ASP-DAC, 2006)

Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems. - Lap-Fai Leung; Chi-Ying Tsui (DAC, 2006)

High performance single clock cycle CMOS comparator. - Hing-mo Lam; Chi-Ying Tsui (ISCAS, 2006)

Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time. - Feng Liu; Chi-Ying Tsui (ISCAS, 2006)

A charge based computation system and control strategy for energy harvesting applications. - Hui Shao; Chi-Ying Tsui; Wing-Hung Ki (ISCAS, 2006)

High efficiency cross-coupled doubler with no reversion loss. - Feng Su; Wing-Hung Ki; Chi-Ying Tsui (ISCAS, 2006)

A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications. - Jie Jin; Chi-Ying Tsui (ISLPED, 2006)

Low Complexity SST Viterbi Decoder. - Jin Jie; Chi-Ying Tsui (VTC Fall, 2006)

Integrated Low-Loss CMOS Active Rectifier for Wirelessly Powered Devices. - Yat-Hei Lam; Wing-Hung Ki; Chi-Ying Tsui (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Single-Chip UHF RFID reader in 0.18- μm CMOS. - Wenting Wang; Shuzuo Lou; Kay W. C. Chui; Sujiang Rong; Chi Fung Lok; Hui Zheng 002; Hin-Tat Chan; Adam S. W. Man; Howard C. Luong; Vincent Kin Nang Lau; Chi-Ying Tsui (CICC, 2007)

Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands. - Lap-Fai Leung; Chi-Ying Tsui (DAC, 2007)

A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic. - Hui Shao; Chi-Ying Tsui (ESSCIRC, 2007)

A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications. - Chao Lu 005; Chi-Ying Tsui; Wing-Hung Ki (ISCAS, 2007)

Design and Implementation of a Low-power Baseband-system for RFID Tag. - Adam S. W. Man; Edward S. Zhang; Hin-Tat Chan; Vincent K. N. Lau; Chi-Ying Tsui; Howard C. Luong (ISCAS, 2007)

An Inductor-less Micro Solar Power Management System Design for Energy Harvesting Applications. - Hui Shao; Chi-Ying Tsui; Wing-Hung Ki (ISCAS, 2007)

Vibration energy scavenging and management for ultra low power applications. - Chao Lu 005; Chi-Ying Tsui; Wing-Hung Ki (ISLPED, 2007)

A micro power management system and maximum output power control for solar energy harvesting applications. - Hui Shao; Chi-Ying Tsui; Wing-Hung Ki (ISLPED, 2007)

A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. - Wei-Feng He; Meng-Lian Zhao; Chi-Ying Tsui; Zhi-Gang Mao (VLSI Design, 2007)

A mux-based High-Performance Single-Cycle CMOS Comparator. - Hing Mo Lam; Chi-Ying Tsui (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications. - Jun Yi; Wing-Hung Ki; Chi-Ying Tsui (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Corrections to "Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications" [Jan 07 153-166]. - Jun Yi; Wing-Hung Ki; Chi-Ying Tsui (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition. - Jie Jin; Chi-Ying Tsui (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Threshold Voltage Start-up Boost Converter for Sub-mA Applications. - Ngok-Man Sze; Wing-Hung Ki; Chi-Ying Tsui (DELTA, 2008)

Integrated single-inductor dual-input dual-output boost converter for energy harvesting applications. - Ngok-Man Sze; Feng Su; Yat-Hei Lam; Wing-Hung Ki; Chi-Ying Tsui (ISCAS, 2008)

An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting. - Jun Yi; Feng Su; Yat-Hei Lam; Wing-Hung Ki; Chi-Ying Tsui (ISCAS, 2008)

A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes. - Jie Jin; Chi-Ying Tsui (ISLPED, 2008)

A Low Energy Two-Step Successive Approximation Algorithm for ADC Design. - Ricky Yiu-kee Choi; Chi-Ying Tsui (ISQED, 2008)

Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping. - Chi-Ying Tsui; Robert Yi-Ching Au; Ricky Yiu-kee Choi (Integr., 2008)

Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications. - Feng Su; Wing-Hung Ki; Chi-Ying Tsui (IEEE J. Solid State Circuits, 2008)

A Single-Chip UHF RFID Reader in 0.18 µm CMOS Process. - Wenting Wang; Shuzuo Lou; Kay W. C. Chui; Sujiang Rong; Chi Fung Lok; Hui Zheng 002; Hin-Tat Chan; Sau-Wing Man; Howard C. Luong; Vincent K. N. Lau; Chi-Ying Tsui (IEEE J. Solid State Circuits, 2008)

Low energy level converter design for sub-Vth logics. - Hui Shao; Chi-Ying Tsui (ASP-DAC, 2009)

An inductor-less MPPT design for light energy harvesting systems. - Hui Shao; Chi-Ying Tsui; Wing-Hung Ki (ASP-DAC, 2009)

Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition. - Jie Jin; Chi-Ying Tsui (ISCAS, 2009)

A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications. - Hui Shao; Chi-Ying Tsui; Wing-Hung Ki (ISLPED, 2009)

Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation. - Feng Su; Wing-Hung Ki; Chi-Ying Tsui (IEEE J. Solid State Circuits, 2009)

The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control. - Hui Shao; Chi-Ying Tsui; Wing-Hung Ki (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Maximizing the harvested energy for micro-power applications through efficient MPPT and PMU design. - Hui Shao; Chi-Ying Tsui; Wing-Hung Ki (ASP-DAC, 2010)

System level power optimizations for EPC RFID tags to improve sensitivity using load power shaping and operation scheduling. - Yunxiao Ling; Jun Yi; Chi-Ying Tsui; Wing-Hung Ki (ISCAS, 2010)

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor. - Jun Yin 001; Jun Yi; Man Kay Law; Yunxiao Ling; Man Chiu Lee; Kwok Ping Ng; Bo Gao; Howard C. Luong; Amine Bermak; Mansun Chan; Wing-Hung Ki; Chi-Ying Tsui; et al. (ISSCC, 2010)

A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control. - Hui Shao; Chi-Ying Tsui; Wing-Hung Ki (VLSI-SoC, 2010)

A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor. - Jun Yin 001; Jun Yi; Matthew K. Law; Yunxiao Ling; Man Chiu Lee; Kwok Ping Ng; Bo Gao; Howard C. Luong; Amine Bermak; Mansun Chan; Wing-Hung Ki; Chi-Ying Tsui; et al. (IEEE J. Solid State Circuits, 2010)

An Energy Efficient Layered Decoding Architecture for LDPC Decoder. - Jie Jin; Chi-Ying Tsui (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Joint Routing and Sleep Scheduling for Lifetime Maximization of Wireless Sensor Networks. - Feng Liu; Chi-Ying Tsui; Ying Jun Zhang (IEEE Trans. Wirel. Commun., 2010)

A thermal-aware application specific routing algorithm for Network-on-Chip design. - Zhiliang Qian; Chi-Ying Tsui (ASP-DAC, 2011)

Efficient iterative receiver for LDPC coded wireless IPTV system. - YouZhe Fan; James She; Chi-Ying Tsui (ICIP, 2011)

A low-complexity image compression algorithm for Address-Event Representation (AER) PWM image sensors. - Denis Guangyin Chen; Amine Bermak; Chi-Ying Tsui (ISCAS, 2011)

Design and analysis of on-chip charge pumps for micro-power energy harvesting applications. - Wing-Hung Ki; Yan Lu 002; Feng Su; Chi-Ying Tsui (VLSI-SoC, 2011)

Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications. - Wing-Hung Ki; Yan Lu 002; Feng Su; Chi-Ying Tsui (VLSI-SoC (Selected Papers), 2011)

A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources. - Zhiliang Qian; Ying Fei Teh; Chi-Ying Tsui (VLSI-SoC, 2011)

A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme. - Ying Fei Teh; Zhiliang Qian; Chi-Ying Tsui (VLSI-SoC, 2011)

Low energy multi-stage level converter for sub-threshold logic. - Hui Shao; Xing Li 004; Chi-Ying Tsui (IET Comput. Digit. Tech., 2011)

Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications. - Chao Lu 005; Chi-Ying Tsui; Wing-Hung Ki (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture. - Zhiliang Qian; Paul Bogdan; Guopeng Wei; Chi-Ying Tsui; Radu Marculescu (CODES+ISSS, 2012)

A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels. - Zhiliang Qian; Ying Fei Teh; Chi-Ying Tsui (DATE, 2012)

A novel offset cancellation technique for dynamic comparator latch. - Ricky Yiu-kee Choi; Chi-Ying Tsui (MWSCAS, 2012)

Low-Complexity Rotated QAM Demapper for the Iterative Receiver Targeting DVB-T2 Standard. - YouZhe Fan; Chi-Ying Tsui (VTC Fall, 2012)

SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model. - Zhiliang Qian; Da-Cheng Juan; Paul Bogdan; Chi-Ying Tsui; Diana Marculescu; Radu Marculescu (DATE, 2013)

Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial). - Zhiliang Qian; Paul Bogdan; Chi-Ying Tsui; Radu Marculescu (ICCAD, 2013)

A diamond search windowbased adaptive search range algorithm. - Luheng Jia; Oscar C. Au; Chi-Ying Tsui; Yongfang Shi; Rui Ma; Hong Zhang 024 (ICME Workshops, 2013)

A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices. - Yan Lu 002; Xing Li 004; Wing-Hung Ki; Chi-Ying Tsui; C. Patrick Yue (ISSCC, 2013)

Energy Harvesting and Power Delivery for Implantable Medical Devices. - Chi-Ying Tsui; Xing Li 004; Wing-Hung Ki (Found. Trends Electron. Des. Autom., 2013)

A comprehensive and accurate latency model for Network-on-Chip performance analysis. - Zhiliang Qian; Da-Cheng Juan; Paul Bogdan; Chi-Ying Tsui; Diana Marculescu; Radu Marculescu (ASP-DAC, 2014)

Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis. - Yuankun Xue; Zhiliang Qian; Paul Bogdan; Fan Ye 001; Chi-Ying Tsui (DAC, 2014)

Low-latency MAP demapper architecture for coded modulation with iterative decoding. - YouZhe Fan; Chi-Ying Tsui (ISCAS, 2014)

An adaptive wireless powering and data telemetry system for optic nerve stimulation. - Xing Li 004; Yan Lu 002; Chi-Ying Tsui; Wing-Hung Ki (ISCAS, 2014)

A fast intermode decision algorithm based on analysis of inter prediction residual. - Luheng Jia; Oscar C. Au; Chi-Ying Tsui; Wei Dai 002; Pengfei Wan 001 (MMSP, 2014)

An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms. - Yuankun Xue; Zhiliang Qian; Guopeng Wei; Paul Bogdan; Chi-Ying Tsui; Radu Marculescu (NOCS, 2014)

A 13.56MHz wireless power transfer system with reconfigurable resonant regulating rectifier and wireless power control for implantable medical devices. - Xing Li 004; Chi-Ying Tsui; Wing-Hung Ki (VLSIC, 2014)

An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation. - YouZhe Fan; Chi-Ying Tsui (IEEE Trans. Signal Process., 2014)

A Novel Single-Inductor Dual-Input Dual-Output DC-DC Converter With PWM Control for Solar Energy Harvesting System. - Hui Shao; Xing Li 004; Chi-Ying Tsui; Wing-Hung Ki (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Low-latency list decoding of polar codes with double thresholding. - YouZhe Fan; Ji Chen; ChenYang Xia; Chi-Ying Tsui; Jie Jin; Hui Shen 006; Bin Li 013 (ICASSP, 2015)

A fast variable block size motion estimation algorithm with refined search range for a two-layer data reuse scheme. - Luheng Jia; Chi-Ying Tsui; Oscar C. Au; Amin Zheng (ISCAS, 2015)

UHF energy harvesting system using reconfigurable rectifier for wireless sensor network. - Xing Li 004; Chi-Ying Tsui; Wing-Hung Ki (ISCAS, 2015)

12.8 Wireless power transfer system using primary equalizer for coupling- and load-range extension in bio-implant applications. - Xing Li 004; Chi-Ying Tsui; Wing-Hung Ki (ISSCC, 2015)

Low complexity belief propagation polar code decoder. - Syed Mohsin Abbas; YouZhe Fan; Ji Chen; Chi-Ying Tsui (SiPS, 2015)

Message from the technical program chairs. - Youngsoo Shin; Chi-Ying Tsui (VLSI-SoC, 2015)

Low Complexity Belief Propagation Polar Code Decoders. - Syed Mohsin Abbas; YouZhe Fan; Ji Chen; Chi-Ying Tsui (CoRR, 2015)

A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices. - Xing Li 004; Chi-Ying Tsui; Wing-Hung Ki (IEEE J. Solid State Circuits, 2015)

Reconfigurable Resonant Regulating Rectifier With Primary Equalization for Extended Coupling- and Loading-Range in Bio-Implant Wireless Power Transfer. - Xing Li 004; Xiaodong Meng; Chi-Ying Tsui; Wing-Hung Ki (IEEE Trans. Biomed. Circuits Syst., 2015)

Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier. - Xing Li 004; Chi-Ying Tsui; Wing-Hung Ki (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels. - Zhiliang Qian; Syed Mohsin Abbas; Chi-Ying Tsui (IEEE Trans. Very Large Scale Integr. Syst., 2015)

LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. - Jingyang Zhu; Zhiliang Qian; Chi-Ying Tsui (ASP-DAC, 2016)

Low-Complexity List Successive-Cancellation Decoding of Polar Codes Using List Pruning. - Ji Chen; YouZhe Fan; ChenYang Xia; Chi-Ying Tsui; Jie Jin; Kai Chen 013; Bin Li 013 (GLOBECOM, 2016)

Hardware decoders for polar codes: An overview. - Pascal Giard; Gabi Sarkis; Alexios Balatsoukas-Stimming; YouZhe Fan; Chi-Ying Tsui; Andreas Peter Burg; Claude Thibeault; Warren J. Gross (ISCAS, 2016)

An indoor solar energy harvesting system using dual mode SIDO converter with fully digital time-based MPPT. - Xiaodong Meng; Xing Li 004; Chi-Ying Tsui; Wing-Hung Ki (ISCAS, 2016)

A WLAN 2.4-GHz RF energy harvesting system with reconfigurable rectifier for wireless sensor network. - Zizhen Zeng; Xing Li 004; Amine Bermak; Chi-Ying Tsui; Wing-Hung Ki (ISCAS, 2016)

A low-power chopper bandpass amplifier for biopotential sensors. - Jiawei Zheng; Wing-Hung Ki; Chi-Ying Tsui (ISCAS, 2016)

21.7 A 6.78MHz 6W wireless power receiver with a 3-level 1× / ½ × / 0× reconfigurable resonant regulating rectifier. - Lin Cheng 001; Wing-Hung Ki; Tat-To Wong; Tak-Sang Yim; Chi-Ying Tsui (ISSCC, 2016)

Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. - Syed Mohsin Abbas; Chi-Ying Tsui (VLSI-SoC, 2016)

Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO. - Syed Mohsin Abbas; Chi-Ying Tsui (VLSI-SoC (Selected Papers), 2016)

BiLink: A high performance NoC router architecture using bi-directional link with double data rate. - Jingyang Zhu; Zhiliang Qian; Chi-Ying Tsui (Integr., 2016)

A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes. - YouZhe Fan; ChenYang Xia; Ji Chen; Chi-Ying Tsui; Jie Jin; Hui Shen 006; Bin Li 013 (IEEE J. Sel. Areas Commun., 2016)

A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures. - Zhiliang Qian; Da-Cheng Juan; Paul Bogdan; Chi-Ying Tsui; Diana Marculescu; Radu Marculescu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling. - Zhiliang Qian; Paul Bogdan; Chi-Ying Tsui; Radu Marculescu (ACM Trans. Design Autom. Electr. Syst., 2016)

A wireless power receiver with a 3-level reconfigurable resonant regulating rectifier for mobile-charging applications. - Lin Cheng 001; Wing-Hung Ki; Chi-Ying Tsui (ASP-DAC, 2017)

BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques. - Jingyang Zhu; Zhiliang Qian; Chi-Ying Tsui (ASP-DAC, 2017)

An implementation of list successive cancellation decoder with large list size for polar codes. - ChenYang Xia; YouZhe Fan; Ji Chen; Chi-Ying Tsui; ChongYang Zeng; Jie Jin; Bin Li 013 (FPL, 2017)

Concatenated LDPC-polar codes decoding through belief propagation. - Syed Mohsin Abbas; YouZhe Fan; Ji Chen; Chi-Ying Tsui (ISCAS, 2017)

Dual transduction Gas sensor based on a surface acoustic wave resonator. - Feng Gao; Amine Bermak; Chi-Ying Tsui; Farid Boussaïd (ISCAS, 2017)

A low-offset dynamic comparator with area-efficient and low-power offset cancellation. - Xiaopeng Zhong; Amine Bermak; Chi-Ying Tsui (VLSI-SoC, 2017)

A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier. - Lin Cheng 001; Wing-Hung Ki; Chi-Ying Tsui (IEEE J. Solid State Circuits, 2017)

Wireless Power Transfer System With ΣΔ-Modulated Transmission Power and Fast Load Response for Implantable Medical Devices. - Xing Li 004; Yin-Ping Li; Chi-Ying Tsui; Wing-Hung Ki (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Chopper Capacitively Coupled Instrumentation Amplifier Capable of Handling Large Electrode Offset for Biopotential Recordings. - Jiawei Zheng; Wing-Hung Ki; Langyu Hu; Chi-Ying Tsui (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder. - Syed Mohsin Abbas; YouZhe Fan; Ji Chen; Chi-Ying Tsui (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Simplified PWM Controller for Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier. - Lin Cheng 001; Xinyuan Ge; Wing-Hung Ki; Chi-Ying Tsui (APCCAS, 2018)

A 40.68MHz Active Rectifier with Hybrid Delay Compensation Scheme. - Langyu Hu; Lin Cheng 001; Yuan Yao; Tak-Sang Yim; Wing-Hung Ki; Chi-Ying Tsui (APCCAS, 2018)

Polyimide-Based Flexible 3-Coil Inductive Link Design and Optimization. - Yuan Yao; Xiaodong Meng; Chi-Ying Tsui; Wing-Hung Ki (APCCAS, 2018)

A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization. - Xizi Chen; Jingbo Jiang; Jingyang Zhu; Chi-Ying Tsui (ASP-DAC, 2018)

SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity. - Jingyang Zhu; Jingbo Jiang; Xizi Chen; Chi-Ying Tsui (DATE, 2018)

An Indoor Solar Energy Harvester with Ultra-Low-Power Reconfigurable Power-On-Reset-Styled Voltage Detector. - Xiaodong Meng; Xing Li 004; Yuan Yao; Chi-Ying Tsui; Wing-Hung Ki (ISCAS, 2018)

On Path Memory in List Successive Cancellation Decoder of Polar Codes. - ChenYang Xia; YouZhe Fan; Ji Chen; Chi-Ying Tsui (ISCAS, 2018)

Room-Temperature Dual-mode CMOS Gas-FET Sensor for Diabetes Detection. - Qian Yu; Farid Boussaïd; Amine Bermak; Chi-Ying Tsui (ISCAS, 2018)

A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge Detection. - Xiaopeng Zhong; Qian Yu; Amine Bermak; Chi-Ying Tsui; May-Kay Law (VLSI Circuits, 2018)

A 10.6 pJ⋅K2 Resolution FoM Temperature Sensor Using Astable Multivibrator. - Bo Wang 012; Man-Kay Law; Chi-Ying Tsui; Amine Bermak (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Analysis and Design of a Ripple Reduction Chopper Bandpass Amplifier. - Jiawei Zheng; Wing-Hung Ki; Chi-Ying Tsui (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Fully Integrated Analog Front End for Biopotential Signal Sensing. - Jiawei Zheng; Wing-Hung Ki; Chi-Ying Tsui (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Low-Power Compression-Based CMOS Image Sensor With Microshift-Guided SAR ADC. - Xiaopeng Zhong; Bo Zhang 025; Amine Bermak; Chi-Ying Tsui; Man-Kay Law (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes. - Mahsa Mousavi; YouZhe Fan; Chi-Ying Tsui; Jie Jin; Bin Li 013; Hui Shen 006 (IEEE Trans. Signal Process., 2018)

A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size. - ChenYang Xia; Ji Chen; YouZhe Fan; Chi-Ying Tsui; Jie Jin; Hui Shen 006; Bin Li 013 (IEEE Trans. Signal Process., 2018)

CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation. - Xizi Chen; Jingyang Zhu; Jingbo Jiang; Chi-Ying Tsui (ASP-DAC, 2019)

A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes. - ChenYang Xia; YouZhe Fan; Chi-Ying Tsui (ISCAS, 2019)

A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques. - Lin Cheng 001; Xinyuan Ge; Wai Chiu Ng; Wing-Hung Ki; Jiawei Zheng; Tsz Fai Kwok; Chi-Ying Tsui; Ming Liu 022 (VLSI Circuits, 2019)

A 2.2μW 600kHz Frequency-Locked Relaxation Oscillator with 0.046%/V Voltage and 48.69ppm/°C Temperature Stability for IoT Sensor Node Applications. - Xiaodong Meng; Xing Li 004; Xiaopeng Zhong; Yuan Yao; Chi-Ying Tsui; Wing-Hung Ki (VLSI Circuits, 2019)

SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup. - Xizi Chen; Jingbo Jiang; Jingyang Zhu; Chi-Ying Tsui (Integr., 2019)

Design of Sub-Gigahertz Reconfigurable RF Energy Harvester From -22 to 4 dBm With 99.8% Peak MPPT Power Efficiency. - Zizhen Zeng; Shanpu Shen; Xiaopeng Zhong; Xing Li 004; Chi-Ying Tsui; Amine Bermak; Ross D. Murch; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2019)

Microshift: An Efficient Image Compression Algorithm for Hardware. - Bo Zhang 025; Pedro V. Sander; Chi-Ying Tsui; Amine Bermak (IEEE Trans. Circuits Syst. Video Technol., 2019)

A -12.3 dBm UHF Passive RFID Sense Tag for Grid Thermal Monitoring. - Bo Wang 012; Man-Kay Law; Jun Yi; Chi-Ying Tsui; Amine Bermak (IEEE Trans. Ind. Electron., 2019)

A New Rate-Complexity-Distortion Model for Fast Motion Estimation Algorithm in HEVC. - Luheng Jia; Chi-Ying Tsui; Oscar C. Au; Kebin Jia (IEEE Trans. Multim., 2019)

Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications. - Lin Cheng 001; Xinyuan Ge; Wai Chiu Ng; Wing-Hung Ki; Jiawei Zheng; Tsz Fai Kwok; Chi-Ying Tsui; Ming Liu 022 (ASP-DAC, 2020)

Tight Compression: Compressing CNN Model Tightly Through Unstructured Pruning and Simulated Annealing Based Permutation. - Xizi Chen; Jingyang Zhu; Jingbo Jiang; Chi-Ying Tsui (DAC, 2020)

A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique. - Lin Cheng 001; Xinyuan Ge; Wai Chiu Ng; Wing-Hung Ki; Jiawei Zheng; Tsz Fai Kwok; Chi-Ying Tsui; Ming Liu 022 (IEEE J. Solid State Circuits, 2020)

A Fully Dynamic Multi-Mode CMOS Vision Sensor With Mixed-Signal Cooperative Motion Sensing and Object Segmentation for Adaptive Edge Computing. - Xiaopeng Zhong; Man-Kay Law; Chi-Ying Tsui; Amine Bermak (IEEE J. Solid State Circuits, 2020)

A 40.68-MHz Active Rectifier With Hybrid Adaptive On/Off Delay-Compensation Scheme for Biomedical Implantable Devices. - Lin Cheng 001; Xinyuan Ge; Langyu Hu; Yuan Yao; Wing-Hung Ki; Chi-Ying Tsui (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Low-Power Motion Estimation Architecture for HEVC Based on a New Sum of Absolute Difference Computation. - Luheng Jia; Chi-Ying Tsui; Oscar C. Au; Kebin Jia (IEEE Trans. Circuits Syst. Video Technol., 2020)

Construction of Multi-Kernel Polar Codes With Kernel Substitution. - ChenYang Xia; Chi-Ying Tsui; YouZhe Fan (IEEE Wirel. Commun. Lett., 2020)

A Reconfigurable Winograd CNN Accelerator with Nesting Decomposition Algorithm for Computing Convolution with Large Filters. - Jingbo Jiang; Xizi Chen; Chi-Ying Tsui (CoRR, 2021)

TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network. - Xiaomeng Wang; Xuejiao Liu; Xianghong Hu; Xiaopeng Zhong; Xizi Chen; Yu Liu 007; Patrick Kong; Fengshi Tian; Chi-Ying Tsui (AICAS, 2022)

FedDQ: Communication-Efficient Federated Learning with Descending Quantization. - Linping Qu; Shenghui Song 001; Chi-Ying Tsui (GLOBECOM, 2022)

A 16-bit Encrypted On-chip Embedded System for Implantable Medical Devices. - Sayan Sarkar; Jingbo Jiang; Wing-Hung Ki; Chi-Ying Tsui (ISCAS, 2022)

Design Strategy of Off-Resonant Tertiary Coils for Uplink Detection in Biomedical Implants. - Sayan Sarkar; Yuan Yao; Wing-Hung Ki; Chi-Ying Tsui (ISCAS, 2022)

Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications. - Soumitra Pal 002; Wing-Hung Ki; Chi-Ying Tsui (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

SNNOpt: An Application-Specific Design Framework for Spiking Neural Networks. - Jingyu He; Ziyang Shen; Fengshi Tian; Jinbo Chen; Jie Yang 033; Mohamad Sawan; Hsiang-Ting Chen; Paul Bogdan; Chi-Ying Tsui (AICAS, 2023)

Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System. - Fengshi Tian; Xiaomeng Wang; Jinbo Chen; Jie Yang 033; Mohamad Sawan; Chi-Ying Tsui; Kwang-Ting (Tim) Cheng (AICAS, 2023)

RVComp: Analog Variation Compensation for RRAM-Based in-Memory Computing. - Jingyu He; Yucong Huang; Miguel Angel Lastras-Montaño; Terry Tao Ye; Chi-Ying Tsui; Kwang-Ting Cheng (ASP-DAC, 2023)

A Primary Driver with Real-Time Resonance Tracking for Wireless-Powered Implantable Medical Devices. - Xiaodong Meng; Xing Li 004; Yuan Yao; Chi-Ying Tsui; Wing-Hung Ki (A-SSCC, 2023)

NOLS: A Near-sensor On-chip Learning System with Direct Feedback Alignment for Personalized Wearable Heart Health Monitoring. - Fengshi Tian; Shiqi Zhao; Jingyu He; Jinbo Chen; Xiaomeng Wang; Jie Yang 033; Mohamad Sawan; Chi-Ying Tsui; Kwang-Ting (Tim) Cheng (BioCAS, 2023)

Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification. - Xizi Chen; Rui Pan; Xiaomeng Wang; Fengshi Tian; Chi-Ying Tsui (DAC, 2023)

AutoDCIM: An Automated Digital CIM Compiler. - Jia Chen; Fengbin Tu; Kunming Shao; Fengshi Tian; Xiao Huo; Chi-Ying Tsui; Kwang-Ting Cheng (DAC, 2023)

BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare. - Fengshi Tian; Xiaomeng Wang; Jinbo Chen; Jiakun Zheng; Hui Wu 010; Xuejiao Liu; Fengbin Tu; Jie Yang 033; Mohamad Sawan; Chi-Ying Tsui; Kwang-Ting (Tim) Cheng (ESSCIRC, 2023)

Step-GRAND: A Low Latency Universal Soft-Input Decoder. - Syed Mohsin Abbas; Chi-Ying Tsui; Marwan Jalaleddine; Warren J. Gross (GLOBECOM (Workshops), 2023)

Accelerating Large Kernel Convolutions with Nested Winograd Transformation. - Jingbo Jiang; Xizi Chen; Chi-Ying Tsui (VLSI-SoC (Selected Papers), 2023)

Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications. - Soumitra Pal 002; Gajendranath Chowdary; Wing-Hung Ki; Chi-Ying Tsui (IEEE Access, 2023)

A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications. - Xiaomeng Wang; Fengshi Tian; Xizi Chen; Jiakun Zheng; Xuejiao Liu; Fengbin Tu; Jie Yang 033; Mohamad Sawan; Kwang-Ting Cheng; Chi-Ying Tsui (CoRR, 2023)

Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation. - Xizi Chen; Jingyang Zhu; Jingbo Jiang; Chi-Ying Tsui (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad. - Xianghong Hu; Xuejiao Liu; Yu Liu 007; Haowei Zhang; Xijie Huang; Xihao Guan; Luhong Liang; Chi-Ying Tsui; Xiaoming Xiong; Kwang-Ting Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Time Domain Analysis of WPT System with Parallel Resonant Secondary Stage Driving Rectifier Load. - Wing-Hung Ki; Yuan Yao; Chi-Ying Tsui (APCCAS, 2024)

RWriC: A Dynamic Writing Scheme for Variation Compensation for RRAM-based In-Memory Computing. - Yucong Huang; Jingyu He; Kwang-Ting (Tim) Cheng; Chi-Ying Tsui; Terry Tao Ye (DAC, 2024)

AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator Using Adaptive Posit. - Jingyu He; Fengbin Tu; Kwang-Ting Cheng; Chi-Ying Tsui (DATE, 2024)

Design of a Fully Integrated Hysteretic Controlled Reconfigurable Transmitter for Bioimplants. - Sayan Sarkar; Yuan Yao; Wing-Hung Ki; Chi-Ying Tsui (EMBC, 2024)

ReSCIM: Variation-Resilient High Weight-Loading Bandwidth In-Memory Computation Based on Fine-Grained Hybrid Integration of Multi-Level ReRAM and SRAM Cells. - Xiaomeng Wang; Jingyu He; Kunming Shao; Jiakun Zheng; Fengshi Tian; Kwang-Ting (Tim) Cheng; Chi-Ying Tsui (ICCAD, 2024)

Time Domain Analysis of Secondary Stage With Series Resonance Driving Rectifier Load. - Wing-Hung Ki; Yuan Yao; Chi-Ying Tsui (ISCAS, 2024)

Adaptive Digitally-Controlled Active Rectifier-Based Receiver for Bioimplants. - Sayan Sarkar; Yuan Yao; Wing-Hung Ki; Chi-Ying Tsui (ISCAS, 2024)

BOLS: A Bionic Sensor-direct On-chip Learning System with Direct-Feedback-Through-Time for Personalized Wearable Health Monitoring. - Fengshi Tian; Jiakun Zheng; Jingyu He; Jinbo Chen; Xiaomeng Wang; Chaoming Fang; Jie Yang 033; Mohamad Sawan; Chi-Ying Tsui; Kwang-Ting Cheng (ISCAS, 2024)

How Robust is Federated Learning to Communication Error? A Comparison Study Between Uplink and Downlink Channels. - Linping Qu; Shenghui Song 001; Chi-Ying Tsui; Yuyi Mao (WCNC, 2024)

FedAQ: Communication-Efficient Federated Edge Learning via Joint Uplink and Downlink Adaptive Quantization. - Linping Qu; Shenghui Song 001; Chi-Ying Tsui (CoRR, 2024)

Partial Knowledge Distillation for Alleviating the Inherent Inter-Class Discrepancy in Federated Learning. - Xiaoyu Gan; Xizi Chen; Jingyang Zhu; Xiaomeng Wang; Jingbo Jiang; Chi-Ying Tsui (CoRR, 2024)

A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices. - Xiaodong Meng; Xing Li 004; Chi-Ying Tsui; Wing-Hung Ki; Weiqiang Liu 001 (IEEE J. Solid State Circuits, 2024)

Energy-Efficient Channel Decoding for Wireless Federated Learning: Convergence Analysis and Adaptive Design. - Linping Qu; Yuyi Mao; Shenghui Song 001; Chi-Ying Tsui (IEEE Trans. Wirel. Commun., 2024)

Analysis of Off-Resonant Flexible Tertiary Coils in Biomedical Implants for Back Telemetry Detection. - Sayan Sarkar; Yuan Yao; Wing-Hung Ki; Chi-Ying Tsui (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

E-NPU: A 34 126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-Model In-Memory Inference/Training for Personalized Medical Wearables. - Fengshi Tian; Jinbo Chen; Kunming Shao; Zilu Liu; Jiakun Zheng; Hui Wu 010; Chaoming Fang; Xiaomeng Wang; Ziyang Shen; Pingcheng Dong; Yuan Yao; Xuliang Wang; et al. (CICC, 2025)

SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis. - Kunming Shao; Fengshi Tian; Xiaomeng Wang; Jiakun Zheng; Jia Chen; Jingyu He; Hui Wu 010; Jinbo Chen; Xihao Guan; Yi Deng; Fengbin Tu; Jie Yang 033; et al. (DATE, 2025)

DPE-CIM: Compute-In-Memory Accelerator using Dynamic Posit Encoding and Speculative Alignment. - Jingyu He; Kwang-Ting Cheng; Chi-Ying Tsui (ISCAS, 2025)

A Dual-Mode One-stage R3 Rectifier with Wide Loading Range for Implantable Medical Devices. - Tsz Fai Kwok; Yuan Yao; Pok Man Leung; Wing-Hung Ki; Chi-Ying Tsui (ISCAS, 2025)

Analysis and Prevention of Coupling-Dependent Data Flipping in Series-Series Resonant Wireless Power Transfer Systems. - Yuan Yao; Sayan Sarkar; Fengshi Tian; Wing-Hung Ki; Chi-Ying Tsui; Yang Liu (ISCAS, 2025)

A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination. - Liang Zhao; Kunming Shao; Fengshi Tian; Kwang-Ting (Tim) Cheng; Chi-Ying Tsui; Yi Zou (ISCAS, 2025)

NeuroEye: A 54.59mW, 12200FPS Event-Driven Near-Sensor Eye-Tracking Processor with Pipelined Spatial-Temporal Spike-Streaming. - Jiakun Zheng; Fengshi Tian; Jinbo Chen; Chaoming Fang; Yuan Yao; Jie Yang 033; Mohamad Sawan; Kwang-Ting (Tim) Cheng; Chi-Ying Tsui (ISCAS, 2025)

A 28nm 0.22μJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation. - Pingcheng Dong; Yonghao Tan; Xuejiao Liu; Peng Luo; Yu Liu 007; Luhong Liang; Yitong Zhou; Di Pang; Manto Yung; Dong Zhang; Xijie Huang; Shih-Yang Liu; et al. (ISSCC, 2025)

Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding. - Syed Mohsin Abbas; Marwan Jalaleddine; Chi-Ying Tsui; Warren J. Gross (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Hysteresis-Dependent Synchronized Load Shift Keying and Reconfigurable Class-D Power Amplifier-Based Fully Integrated Adaptive Control in Wireless Power Transfer System. - Sayan Sarkar; Yuan Yao; Wing-Hung Ki; Chi-Ying Tsui (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)