All-digital delay-locked loop for 3D-IC die-to-die clock synchronization. - Ching-Che Chung; Chi-Yu Hou (VLSI-DAT, 2014)

An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications. - Ching-Che Chung; Chi-Yu Hou (Microelectron. J., 2017)