An AND-type match-line scheme for high-performance energy-efficient content addressable memories. - Hung-Yu Li; Chia-Cheng Chen; Jinn-Shyan Wang; Chingwei Yeh (IEEE J. Solid State Circuits, 2006)

Comparison of ICC and CCC for assessing agreement for data without and with replications. - Chia-Cheng Chen; Huiman X. Barnhart (Comput. Stat. Data Anal., 2008)

A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. - Yi-Wei Lin; Hao-I Yang; Geng-Cing Lin; Chi-Shin Chang; Ching-Te Chuang; Wei Hwang; Chia-Cheng Chen; Willis Shih; Huan-Shun Huang (ISLPED, 2012)

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. - Chi-Shin Chang; Hao-I Yang; Wei-Nan Liao; Yi-Wei Lin; Nan-Chun Lien; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming-Hsien Tu; Huan-Shun Huang; Yong-Jyun Hu; et al. (ISCAS, 2013)

Assessing agreement with intraclass correlation coefficient and concordance correlation coefficient for data with repeated measures. - Chia-Cheng Chen; Huiman X. Barnhart (Comput. Stat. Data Anal., 2013)

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS. - Ching-Wei Wu; Ming-Hung Chang; Chia-Cheng Chen; Robin Lee; Hung-Jen Liao; Jonathan Chang (A-SSCC, 2014)

Modeling collinear WATs for parametric yield enhancement in semiconductor manufacturing. - Chen-Fu Chien 001; Peng-Chieh Lee; Runliang Dou; Ying-Jen Chen; Chia-Cheng Chen (CASE, 2017)

Adaptive parametric yield enhancement via collinear multivariate analytics for semiconductor intelligent manufacturing. - Chen-Fu Chien 001; Chia-Cheng Chen (Appl. Soft Comput., 2021)

Reconsider Time Series Analysis for Insider Threat Detection. - Chia-Cheng Chen; Hsing-Kuo Pao (IEEE Big Data, 2024)