Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. - Run-Yi Wang; Chia-Cheng Pai; Jun-Jie Wang; Hsiang-Ting Wen; Yu-Cheng Pai; Yao-Wen Chang; James Chien-Mo Li; Jie-Hong Roland Jiang (DAC, 2018)

Test methodology for PCHB/PCFB Asynchronous Circuits. - Ting-Yu Shen; Chia-Cheng Pai; Tsai-Chieh Chen; James Chien-Mo Li; Samuel Pan (ITC, 2018)

DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG. - Shih-An Hsieh; Ying-Hsu Wang; Ting-Yu Shen; Kuan-Yen Huang; Chia-Cheng Pai; Tsai-Chieh Chen; James Chien-Mo Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. - Tsai-Chieh Chen; Chia-Cheng Pai; Yi-Zhan Hsieh; Hsiao-Yin Tseng; Chien-Mo James Li; Tsung-Te Liu; I-Wei Chiu (J. Electron. Test., 2021)