On Construction of an Intelligent Environmental Monitoring System for Healthcare. - Chao-Tung Yang; Jung-Chun Liu; Chi-Jui Liao; Chia-Cheng Wu; Fang-Yie Leu (PDCAT, 2013)

An Environmental Monitoring System for Air Quality Control. - Chao-Tung Yang; Jung-Chun Liu; Yun-Ting Wang; Chia-Cheng Wu; Fang-Yie Leu (ICS, 2014)

Implementation of an environmental quality and harmful gases monitoring system. - Chao-Tung Yang; Jung-Chun Liu; Yun-Ting Wang; Chia-Cheng Wu; Fang-Yie Leu (SMARTCOMP, 2014)

Constructing an optimal spanning tree over a hybrid network with SDN and legacy switches. - Shie-Yuan Wang; Chia-Cheng Wu; Chih-Liang Chou (ISCC, 2015)

Hybridtrace: A traceroute tool for hybrid networks composed of SDN and legacy switches. - Shie-Yuan Wang; Chia-Cheng Wu; Chih-Liang Chou (ISCC, 2016)

Majority logic circuits optimisation by node merging. - Chun-Che Chung; Yung-Chih Chen; Chun-Yao Wang; Chia-Cheng Wu (ASP-DAC, 2017)

Detection of tetracycline using isothermal amplification. - Chia-Cheng Wu; Li-An Wu; Yih-Fan Chen; Lu-Ting Chou (NEMS, 2017)

Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. - Yun-Jui Li; Ching-Yi Huang; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. - Yung-An Lai; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (DATE, 2018)

Logic optimization with considering boolean relations. - Tung-Yuan Lee; Chia-Cheng Wu; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (DATE, 2018)

A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification. - Chia-Cheng Wu; Tung-Yuan Lee; Yung-An Lai; Hsin-Pei Wang; De-Xuan Ji; Yan-Ping Chang; Teng-Chia Wang; Chin-Heng Liu; Chun-Yao Wang; Yung-Chih Chen (ACM Great Lakes Symposium on VLSI, 2018)

Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. - Chia-Cheng Wu; Kung-Han Ho; Juinn-Dar Huang; Chun-Yao Wang (ISVLSI, 2018)

Using range-equivalent circuits for facilitating bounded sequential equivalence checking. - Yung-Chih Chen; Wei-An Ji; Chih-Chung Wang; Ching-Yi Huang; Chia-Cheng Wu; Chia-Chun Lin; Chun-Yao Wang (VLSI-DAT, 2018)

On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses. - Hsin-Pei Wang; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Glitch Key-Gate for Logic Locking. - De-Xuan Ji; Hsiao-Yu Chiang; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2019)

Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. - Chin-Heng Liu; Chia-Chun Lin; Yung-Chih Chen; Chia-Cheng Wu; Chun-Yao Wang; Shigeru Yamashita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. - Chia-Cheng Wu; Yi-Hsiang Hu; Chia-Chun Lin; Yung-Chih Chen; Juinn-Dar Huang; Chun-Yao Wang (ACM J. Emerg. Technol. Comput. Syst., 2021)

DPC-Coded MIMO Multiuser Communications Using RIS with Discrete Phase Shifts. - Chia-Cheng Wu; Hsiao-Feng Lu (ISITA, 2024)