RT-level vector selection for realistic peak power simulation. - Chia-Chien Weng; Ching-Shang Yang; Shi-Yu Huang (ACM Great Lakes Symposium on VLSI, 2007)

Power aware SID-based simulator for embedded multicore DSP subsystems. - Cheng-Yen Lin; Po-Yu Chen; Chun-Kai Tseng; Chung-Wen Huang; Chia-Chieh Weng; Chi-Bang Kuan; Shih-Han Lin; Shi-Yu Huang; Jenq Kuen Lee (CODES+ISSS, 2010)

PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. - Chen-Wei Hsu; Jia-Lu Liao; Shan-Chien Fang; Chia-Chien Weng; Shi-Yu Huang; Wen-Tsan Hsieh; Jen-Chieh Yeh (DAC, 2011)

Black-box leakage power modeling for cell library and SRAM compiler. - Chun-Kai Tseng; Shi-Yu Huang; Chia-Chien Weng; Shan-Chien Fang; Ji-Jan Chen (DATE, 2011)

Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property. - Ruo-Ting Ding; Shi-Yu Huang; Chao-Wen Tzeng; Shan-Chien Fang; Chia-Chien Weng (VLSI-DAT, 2012)

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping. - Pei-Ying Chao; Chao-Wen Tzeng; Shi-Yu Huang; Chia-Chieh Weng; Shan-Chien Fang (IEEE Trans. Very Large Scale Integr. Syst., 2013)