A fully parallel BCH codec with double error correcting capability for NOR flash applications. - Chia-Ching Chu; Yi-Min Lin; Chi-Heng Yang; Hsie-Chia Chang (ICASSP, 2012)

A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications. - Chang-Hung Tsai; Tung-Yu Wu; Shu-Yu Hsu; Chia-Ching Chu; Fang-Ju Ku; Ying-Siou Laio; Chih-Lung Chen; Wing Hung Wong; Hsie-Chia Chang; Chen-Yi Lee (VLSIC, 2014)

Trigger-Based Scheduling and Turning Policy Assignment for Mixed-Traffic Intersection Management. - Chia-Ching Chu; Hsuan Ling; Chung-Wei Lin (IV, 2024)