A new plane-sweep algorithm based on spatial data structure for overlapped rectangles in 2-D plane. - Pei-Yung Hsiao; Chia-Chun Tsai (COMPSAC, 1990)

Generalized terminal connectivity problem for multilayer layout scheme. - Chia-Chun Tsai; Sao-Jie Chen; Wu-Shiung Feng (Comput. Aided Des., 1990)

An H-V Tile-Expansion Router. - Chia-Chun Tsai; Sao-Jie Chen; Wu-Shiung Feng (J. Inf. Sci. Eng., 1990)

A knowledge-based program for compacting mask layout of integrated circuits. - Pei-Yung Hsiao; S. F. Steven Chen; Chia-Chun Tsai; Wu-Shiung Feng (Comput. Aided Des., 1991)

Minimum Partition for the Space Region of VLSI Layout. - Pei-Yung Hsiao; Chiao-Yi Lin; Chia-Chun Tsai (VLSI Design, 1992)

An H-V alternating router. - Chia-Chun Tsai; Sao-Jie Chen; Wu-Shiung Feng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A Linear Time Algorithm for Planar Moat Routing. - Chia-Chun Tsai; Sao-Jie Chen (J. Inf. Sci. Eng., 1994)

Performance driven multiple-source bus synthesis using buffer insertion. - Chia-Chun Tsai; De-Yu Kao; Chung-Kuan Cheng; Ting-Ting Y. Lin (ASP-DAC, 1995)

Performance driven bus buffer insertion. - Chia-Chun Tsai; De-Yu Kao; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Hmap: a fast mapper for EPGAs using extended GBDD hash tables. - Cheng-Hsing Yang; Chia-Chun Tsai; Jan-Ming Ho; Sao-Jie Chen (ACM Trans. Design Autom. Electr. Syst., 1997)

NEWS: a net-even-wiring system for the routing on a multilayer PGA package. - Chia-Chun Tsai; Chwan-Ming Wang; Sao-Jie Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

An Automatic Router for the Pin Grid Array Package. - Shuenn-Shi Chen; Jong-Jang Chen; Sao-Jie Chen; Chia-Chun Tsai (ASP-DAC, 1999)

An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. - Jong-Sheng Cherng; Sao-Jie Chen; Chia-Chun Tsai; Jan-Ming Ho (ASP-DAC, 1999)

An Even Wiring Approach to the Ball Grid Array Package Routing. - Shuenn-Shi Chen; Jong-Jang Chen; Sao-Jie Chen; Chia-Chun Tsai (ICCD, 1999)

Efficient routability check algorithms for segmented channel routing. - Cheng-Hsing Yang; Sao-Jie Chen; Jan-Ming Ho; Chia-Chun Tsai (ACM Trans. Design Autom. Electr. Syst., 2000)

RCGES: Retargetable Code Generation for Embedded Systems. - Trong-Yen Lee; Yang-Hsin Fan; Tsung-Hsun Yang; Chia-Chun Tsai; Wen-Ta Lee; Yuh-Shyan Hwang (ATVA, 2004)

An embedded analog spatial filter design of the current-mode CMOS image sensor. - Pei-Yung Hsiao; Yu-Chun Hsu; Wen-Ta Lee; Chia-Chun Tsai; Chia-Hao Lee (IEEE Trans. Consumer Electron., 2004)

Zero-Skew Driven for RLC Clock Tree Construction in SoC. - Chia-Chun Tsai; Jan-Ou Wu; Chung-Chieh Kuo; Trong-Yen Lee; Wen-Ta Lee (ICITA (1), 2005)

A new CCII-based pipelined analog to digital converter. - Yuh-Shyan Hwang; Lu-Po Liao; Chia-Chun Tsai; Wen-Ta Lee; Trong-Yen Lee; Jiann-Jong Chen (ISCAS (6), 2005)

A new low-power turbo decoder using HDA-DHDD stopping iteration. - Wen-Ta Lee; San-Ho Lin; Chia-Chun Tsai; Trong-Yen Lee; Yuh-Shyan Hwang (ISCAS (2), 2005)

Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. - Chia-Chun Tsai; Jan-Ou Wu; Trong-Yen Lee; Rong-Shue Hsiao (APCCAS, 2006)

Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. - Chia-Chun Tsai; Jan-Ou Wu; Yu-Ting Shieh; Chung-Chieh Kuo; Trong-Yen Lee (APCCAS, 2006)

Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion. - Trong-Yen Lee; Yang-Hsin Fan; Chia-Chun Tsai (ICICIC (2), 2006)

Inductance extraction for general interconnect structures. - Chun-Ying Lai; Shyh-Kang Jeng; Yao-Wen Chang; Chia-Chun Tsai (ISCAS, 2006)

A single chip image sensor embedded smooth spatial filter with A/D conversion. - Chia-Chun Tsai; Huang-Chi Chou; Trong-Yen Lee; Rong-Shue Hsiao (ISCAS, 2006)

Coupling aware RLC-based clock routings for crosstalk minimization. - Chia-Chun Tsai; Jan-Ou Wu; Chien-Wen Kao; Trong-Yen Lee; Rong-Shue Hsiao (ISCAS, 2006)

Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. - Chia-Chun Tsai; Hann-Cheng Huang; Trong-Yen Lee; Wen-Ta Lee; Jan-Ou Wu (J. Inf. Sci. Eng., 2006)

Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems. - Trong-Yen Lee; Yang-Hsin Fan; Yu-Min Cheng; Chia-Chun Tsai; Rong-Shue Hsiao (IIH-MSP, 2007)

An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems. - Trong-Yen Lee; Yang-Hsin Fan; Yu-Min Cheng; Chia-Chun Tsai; Rong-Shue Hsiao (IMECS, 2007)

Zero-Skew Driven Buffered RLC Clock Tree Construction. - Jan-Ou Wu; Chia-Chun Tsai; Chung-Chieh Kuo; Trong-Yen Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Layer assignment considering manufacturability in X-architecture clock tree. - Chia-Chun Tsai; Wei-Shi Lin; Jan-Ou Wu; Chung-Chieh Kuo; Trong-Yen Lee (CIT, 2008)

X-clock routing based on pattern matching. - Chia-Chun Tsai; Chung-Chieh Kuo; Jan-Ou Wu; Trong-Yen Lee; Rong-Shue Hsiao (SoCC, 2008)

GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay. - Chia-Chun Tsai; Jan-Ou Wu; Trong-Yen Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion. - Chia-Chun Tsai; Jan-Ou Wu; Trong-Yen Lee (Circuits Syst. Signal Process., 2009)

A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters. - Chia-Chun Tsai; Kai-Wei Hong; Trong-Yen Lee (J. Circuits Syst. Comput., 2009)

The Design of a Li-ion Battery Charger Based on Multimode LDO Technology. - Chia-Chun Tsai; Chin-Yen Lin; Yuh-Shyan Hwang; Trong-Yen Lee (J. Circuits Syst. Comput., 2009)

Double-via insertion enhanced X-architecture clock routing for reliability. - Chia-Chun Tsai; Chung-Chieh Kuo; Lin-Jeng Gu; Trong-Yen Lee (ISCAS, 2010)

Antenna Violation Avoidance/Fixing for X-clock routing. - Chia-Chun Tsai; Chung-Chieh Kuo; Lin-Jeng Gu; Trong-Yen Lee (ISQED, 2010)

Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems. - Trong-Yen Lee; Che-Cheng Hu; Li-Wen Lai; Chia-Chun Tsai (J. Inf. Sci. Eng., 2010)

Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. - Chia-Chun Tsai; Chung-Chieh Kuo; Trong-Yen Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. - Chung-Chieh Kuo; Chia-Chun Tsai; Trong-Yen Lee (Integr., 2011)

The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B. - Chia-Chun Tsai; Sheng-Bin Dai; Trong-Yen Lee (J. Circuits Syst. Comput., 2011)

Micro fuel cell power management circuit design for portable devices. - Chia-Chun Tsai; Tsung-Ming Liu; Trong-Yen Lee (FSKD, 2012)

Discharge-path-based antenna effect detection and fixing for X-architecture clock tree. - Chia-Chun Tsai; Chung-Chieh Kuo; Feng-Tzu Hsu; Trong-Yen Lee (Integr., 2012)

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. - Kuan-Yu Lin; Hong-Ting Lin; Tsung-Yi Ho; Chia-Chun Tsai (ACM Trans. Design Autom. Electr. Syst., 2012)

Low Complexity Digit-Serial Multiplier over GF(2^m) Using Karatsuba Technology. - Trong-Yen Lee; Min-Jea Liu; Chia-Chen Fan; Chia-Chun Tsai; Haixia Wu (CISIS, 2013)

A reduced Li-Ion battery charger for portable applications. - Chia-Chun Tsai (ICNC, 2013)

Improved PSO based home energy management systems integrated with demand response in a smart grid. - Hong-Tzer Yang; Chiao-Tung Yang; Chia-Chun Tsai; Guan-Jhih Chen; Szu-Yao Chen (CEC, 2015)

Hybrid Architecture Design for Calculating Variable-Length Fourier Transform. - Shin-Chi Lai; Wen-Ho Juang; Yueh-Shu Lee; Shin-Hao Chen; Ke-Horng Chen; Chia-Chun Tsai; Chiung-Hon Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters. - Chia-Chun Tsai (ISVLSI, 2017)

Embedded bus switches on 3D data bus for critical access time reduction. - Chia-Chun Tsai (LASCAS, 2018)

Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period. - Chia-Chun Tsai (ISOCC, 2019)

3D Hand Gesture Recognition for Drone Control in Unity*. - Chia-Chun Tsai; Chih-Chia Kuo; Yen-Lun Chen (CASE, 2020)

SMD LED chips defect detection using a YOLOv3-dense model. - Ssu-Han Chen; Chia-Chun Tsai (Adv. Eng. Informatics, 2021)

A surface defect detection system for golden diamond pineapple based on CycleGAN and YOLOv4. - Ssu-Han Chen; Yu-Wei Lai; Chung-Lun Kuo; Chieh-Yi Lo; Yu-Sung Lin; Yan-Rung Lin; Chih-Hsiang Kang; Chia-Chun Tsai (J. King Saud Univ. Comput. Inf. Sci., 2022)