Floorplan-aware Steiner tree reconstruction for optimal buffer insertion. - Jin-Tai Yan; Chia-Fang Lee; Tzu-Ya Wang (ICECS, 2005)

Timing-Constrained Flexibility-Driven Routing Tree Construction. - Jin-Tai Yan; Yen-Hsiang Chen; Chia-Fang Lee (IEICE Trans. Inf. Syst., 2005)

Timing-constrained yield-driven wire sizing for critical area minimization. - Jin-Tai Yan; Bo-Yi Chiang; Chia-Fang Lee (ISCAS, 2006)

Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. - Jin-Tai Yan; Yen-Hsiang Chen; Chia-Fang Lee; Ming-Ching Huang (ISCAS, 2006)

Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. - Jin-Tai Yan; Chia-Fang Lee; Yen-Hsiang Chen (VLSI Design, 2006)

SDR measurement platform design for FMCW RADAR performance verification. - Juinn-Horng Deng; Pin-Nien Chen; Chia-Fang Lee; Yuan-Feng Chan; Yen-Chung Lin (DSC, 2017)

Loopback Transceiver Self-Calibration Design for Wideband RF Impairments. - Juinn-Horng Deng; Chia-Fang Lee (VTC Spring, 2020)

Self-Calibration of Joint RF Impairments in a Loopback Wideband Transceiver. - Juinn-Horng Deng; Chia-Fang Lee; Meng-Lin Ku; Jeng-Kuang Hwang (IEEE Access, 2020)