Enabling compiler flow for embedded VLIW DSP processors with distributed register files. - Chung-Kai Chen; Ling-Hua Tseng; Shih-Chang Chen; Young-Jia Lin; Yi-Ping You; Chia-Han Lu; Jenq Kuen Lee (LCTES, 2007)

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores. - Yung-Chia Lin; Chia-Han Lu; Chung-Ju Wu; Chung-Lin Tang; Yi-Ping You; Ya-Chiao Moo; Jenq Kuen Lee (J. Signal Process. Syst., 2008)

LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. - Chia-Han Lu; Yung-Chia Lin; Yi-Ping You; Jenq Kuen Lee (Concurr. Comput. Pract. Exp., 2009)

Register spilling via transformed interference equations for PAC DSP architecture. - Chung-Ju Wu; Chia-Han Lu; Jenq Kuen Lee (Concurr. Comput. Pract. Exp., 2014)

Achieving spilling-friendly register file assignment for highly distributed register files. - Chia-Han Lu; Wen-Li Shih; Chung-Ju Wu; Jenq Kuen Lee (J. Supercomput., 2014)

Dynamic SIMD re-convergence with paired-path comparison. - Yun-Chi Huang; Kuan-Chieh Hsu; Wan-shan Hsieh; Chen-Chieh Wang; Chia-Han Lu; Chung-Ho Chen (ISCAS, 2016)