A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; Ian Post; et al. (ISSCC, 2007)

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; et al. (IEEE J. Solid State Circuits, 2008)

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Satoshi Suzuki; Brent R. Carlton; Hyung Seok Kim; et al. (ISSCC, 2012)

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Khoa Minh Nguyen; Hyung-Jin Lee; Ashoke Ravi; et al. (IEEE J. Solid State Circuits, 2013)

A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products. - Chia-Hong Jan; F. Al-amoody; H.-Y. Chang; T. Chang; Y.-W. Chen; N. Dias; Walid M. Hafez; Doug B. Ingerly; M. Jang; Eric Karl; S. K.-Y. Shi; K. Komeyli; et al. (VLSIC, 2015)

Moore's law - predict the unpredictable. - Chia-Hong Jan (VLSI-DAT, 2018)