Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems. - Chia-Hsiang Yang; Yu-Hsuan Lin; Shih-Chun Lin; Tzi-Dar Chiueh (ISCAS (4), 2004)

A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications. - Chia-Hsiang Yang; Dejan Markovic (GLOBECOM, 2008)

A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels. - Chia-Hsiang Yang; Dejan Markovic (ICC, 2008)

A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS. - Chia-Hsiang Yang; Dejan Markovic (ESSCIRC, 2009)

A Flexible DSP Architecture for MIMO Sphere Decoding. - Chia-Hsiang Yang; Dejan Markovic (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

An Energy-Efficient VLSI Architecture for Cognitive Radio Wideband Spectrum Sensing. - Tsung-Han Yu; Chia-Hsiang Yang; Dejan Markovic; Danijela Cabric (GLOBECOM, 2011)

A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection. - Fang-Li Yuan; Chia-Hsiang Yang; Dejan Markovic (GLOBECOM, 2011)

Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection. - Yi-Hsin Shih; Tsan-Jieh Chen; Chia-Hsiang Yang; Herming Chiueh (APSIPA, 2012)

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example. - Chia-Hsiang Yang; Tsung-Han Yu; Dejan Markovic (IEEE J. Solid State Circuits, 2012)

A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios. - Tsung-Han Yu; Chia-Hsiang Yang; Danijela Cabric; Dejan Markovic (IEEE J. Solid State Circuits, 2012)

A 191μW BPSK demodulator for data and power telemetry in biomedical implants. - Li-Lan Wang; Chia-Hsiang Yang; Herming Chiueh (ACM Great Lakes Symposium on VLSI, 2013)

A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control. - Wei-Ming Chen; Herming Chiueh; Tsan-Jieh Chen; Chia-Lun Ho; Chi Jeng; Shun-Ting Chang; Ming-Dou Ker; Chun-Yu Lin 001; Ya-Chun Huang; Chia-Wei Chou; Tsun-Yuan Fan; Ming-Seng Cheng; et al. (ISSCC, 2013)

Power and area reduction in multi-stage addition using operand segmentation. - Ching-Da Chan; Wei-Chang Liu; Chia-Hsiang Yang; Shyh-Jye Jou (VLSI-DAT, 2013)

An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems. - Chiao-En Chen; Chia-Hsiang Yang (CoRR, 2013)

24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia. - Kea-Tiong Tang; Shih-Wen Chiu; Chung-Hung Shih; Chia-Ling Chang; Chia-Min Yang; Da-Jeng Yao; Jen-Huo Wang; Chien-Ming Huang 005; Hsin Chen; Kwuang-Han Chang; Chih-Cheng Hsieh; Ting-Hau Chang; et al. (ISSCC, 2014)

A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. - Wei-Ming Chen; Herming Chiueh; Tsan-Jieh Chen; Chia-Lun Ho; Chi Jeng; Ming-Dou Ker; Chun-Yu Lin 001; Ya-Chun Huang; Chia-Wei Chou; Tsun-Yuan Fan; Ming-Seng Cheng; Yue-Loong Hsin; et al. (IEEE J. Solid State Circuits, 2014)

A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia. - Shih-Wen Chiu; Jen-Huo Wang; Kwuang-Han Chang; Ting-Hau Chang; Chia-Min Wang; Chia-Lin Chang; Chen-Ting Tang; Chien-Fu Chen; Chung-Hung Shih; Han-Wen Kuo; Li-Chun Wang 001; Hsin Chen; et al. (IEEE Trans. Biomed. Circuits Syst., 2014)

A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications. - Chung-Chao Cheng; Jeng-Da Yang; Huang-Chang Lee; Chia-Hsiang Yang; Yeong-Luh Ueng (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 5.4 µW Soft-Decision BCH Decoder for Wireless Body Area Networks. - Chia-Hsiang Yang; Ting-Ying Huang; Mao-Ruei Li; Yeong-Luh Ueng (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 794Mbps 135mW iterative detection and decoding receiver for 4×4 LDPC-coded MIMO systems in 40nm. - Wei-Hsuan Wu; Wei-Cheng Sun; Chia-Hsiang Yang; Yeong-Luh Ueng (VLSIC, 2015)

An 81.6 µW FastICA Processor for Epileptic Seizure Detection. - Chia-Hsiang Yang; Yi-Hsin Shih; Herming Chiueh (IEEE Trans. Biomed. Circuits Syst., 2015)

An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems. - Wei-Cheng Sun; Wei-Hsuan Wu; Chia-Hsiang Yang; Yeong-Luh Ueng (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Systolic Array Based GTD Processor With a Parallel Algorithm. - Chia-Hsiang Yang; Chun-Wei Chou; Chia-Shen Hsu; Chiao-En Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems. - Chiao-En Chen; Yu-Cheng Tsai; Chia-Hsiang Yang (IEEE Trans. Wirel. Commun., 2015)

Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease. - Ting-I Chou; Shih-Wen Chiu; Kwuang-Han Chang; Yi-Ju Chen; Chen-Ting Tang; Chung-Hung Shih; Chih-Cheng Hsieh; Meng-Fan Chang; Chia-Hsiang Yang; Herming Chiueh; Kea-Tiong Tang (BioCAS, 2016)

Error-resilient sequential cells with successive time borrowing for stochastic computing. - Wei-Chang Liu; Ching-Da Chan; Shuo-An Huang; Chi-Wei Lo; Chia-Hsiang Yang; Shyh-Jye Jou (ICASSP, 2016)

sBWT: memory efficient implementation of the hardware-acceleration-friendly Schindler transform for the fast biological sequence mapping. - Chia-Hua Chang; Min-Te Chou; Yi-Chung Wu; Ting-Wei Hong; Yun-Lung Li; Chia-Hsiang Yang; Jui-Hung Hung (Bioinform., 2016)

A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving. - Cheng-Yen Lee; Ping-Hsuan Hsieh; Chia-Hsiang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Integration of energy-recycling logic and wireless power transfer for ultra-low-power implantables. - Hsin-Tzu Lin; Yi-Chung Wu; Ping-Hsuan Hsieh; Chia-Hsiang Yang (ISCAS, 2017)

14.8 A 135mW fully integrated data processor for next-generation sequencing. - Yi-Chung Wu; Jui-Hung Hung; Chia-Hsiang Yang (ISSCC, 2017)

An Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO Detectors. - Wei-Cheng Sun; Chia-Hsiang Yang; Yen-Ming Chen; Yeong-Luh Ueng (VTC Spring, 2017)

A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications. - Mao-Ruei Li; Chia-Hsiang Yang; Yeong-Luh Ueng (IEEE J. Solid State Circuits, 2017)

A 135-mW Fully Integrated Data Processor for Next-Generation Sequencing. - Yi-Chung Wu; Chia-Hua Chang; Jui-Hung Hung; Chia-Hsiang Yang (IEEE Trans. Biomed. Circuits Syst., 2017)

A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems. - Yu-Cheng Tsai; Chiao-En Chen; Chia-Hsiang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 2×2-16×16 Reconfigurable GGMD Processor for MIMO Communication Systems. - Chih-Hsuan Chiang; Shuo-An Huang; Chiao-En Chen; Chia-Hsiang Yang (ISCAS, 2018)

Massive MIMO detection VLSI design. - Chia-Hsiang Yang (VLSI-DAT, 2018)

A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control. - Shuo-An Huang; Kai-Chieh Chang; Horng-Huei Liou; Chia-Hsiang Yang (VLSI Circuits, 2018)

A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. - Yu-Zhe Wang; Yao-Pin Wang; Yi-Chung Wu; Chia-Hsiang Yang (VLSI Circuits, 2018)

Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC). - Tsung-Hsien Lin; Chia-Hsiang Yang; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip. - Ting-I Chou; Kwuang-Han Chang; Jia-Yin Jhang; Shih-Wen Chiu; Guoxing Wang; Chia-Hsiang Yang; Herming Chiueh; Hsin Chen; Chih-Cheng Hsieh; Meng-Fan Chang; Kea-Tiong Tang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems. - Chun-Yu Yeh; Ting-Chung Chu; Chiao-En Chen; Chia-Hsiang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices. - Yu-Chi Lee; Tai-Shih Chi; Chia-Hsiang Yang (AICAS, 2019)

A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training. - Cheng-Hsun Lu; Yi-Chung Wu; Chia-Hsiang Yang (A-SSCC, 2019)

Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. - Yu-Zhe Wang; Jingjie Wu; Shi-Hao Chen; Mango Chia-Tso Chao; Chia-Hsiang Yang (VLSI-DAT, 2019)

A Hardware-Efficient ADMM-Based SVM Training Algorithm for Edge Computing. - Shuo-An Huang; Chia-Hsiang Yang (CoRR, 2019)

A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals. - Yu-Zhe Wang; Yao-Pin Wang; Yi-Chung Wu; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2019)

Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem. - Xin-Hong Qian; Yi-Chung Wu; Tzu-Yi Yang; Cheng-Hsiang Cheng; Hsing-Chien Chu; Wan-Hsueh Cheng; Ting-Yang Yen; Tzu-Han Lin; Yung-Jen Lin; Yu-Chi Lee; Jia-Heng Chang; Shih-Ting Lin; et al. (IEEE Trans. Biomed. Eng., 2019)

An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems. - Yan-Tong Chen; Wei-Cheng Sun; Chung-Chao Cheng; Tsung-Lin Tsai; Yeong-Luh Ueng; Chia-Hsiang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An LDPC-Coded SCMA Receiver With Multi-User Iterative Detection and Decoding. - Wei-Cheng Sun; Yu-Chieh Su; Yeong-Luh Ueng; Chia-Hsiang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems. - Wei-Cheng Sun; Yan-Tong Chen; Chia-Hsiang Yang; Yeong-Luh Ueng (IEEE Trans. Signal Process., 2019)

Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition. - Sung-Hao Wang; Yu-Kai Huang; Ching-Yuan Chen; Chia-Fone Lee; Chia-Hsiang Yang; Chung-Chih Hung; Chien-Hao Liu; Ming-Dou Ker; Chung-Yu Wu (A-SSCC, 2020)

Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax. - Yao-Pin Wang; Chi-Chih Wen; Chen-Chien Kao; Chung-Jung Huang; Der-Zheng Liu; Chia-Hsiang Yang (GLOBECOM, 2020)

A CycleGAN Accelerator for Unsupervised Learning on Mobile Devices. - Yi-Yen Hsieh; Yu-Chi Lee; Chia-Hsiang Yang (ISCAS, 2020)

21.2 A 1.5μJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots. - Chieh Chung; Chia-Hsiang Yang (ISSCC, 2020)

21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing. - Yi-Chung Wu; Yen-Lung Chen; Chung-Hsuan Yang; Chao-Hsi Lee; Chao-Yang Yu; Nian-Shyang Chang; Ling-Chien Chen; Jia-Rong Chang; Chun-Pin Lin; Hung-Lieh Chen; Chi-Shi Chen; Jui-Hung Hung; et al. (ISSCC, 2020)

Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. - Herming Chiueh; Chia-Hsiang Yang; Charles H.-P. Wen; Chao-Guang Yang; Po-Hao Chien; Ching-Yang Hung; Yu-Jui Chen; Yao-Pin Wang; Chin-Fong Chiu; Jer Lin (VLSI-DAT, 2020)

AI Acceleration with RISC-V for Edge Computing. - Chia-Hsiang Yang (VLSI-DAT, 2020)

A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems. - Chi-Chih Wen; Yu-Chi Lee; Yi-Chung Wu; Chen-Chien Kao; Chia-Hsiang Yang (VLSI Circuits, 2020)

A 1.9-mW SVM Processor With On-Chip Active Learning for Epileptic Seizure Control. - Shuo-An Huang; Kai-Chieh Chang; Horng-Huei Liou; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2020)

A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices. - Yu-Chi Lee; Tai-Shih Chi; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2020)

A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices With Speech Intelligibility Enhancement. - Yung-Jen Lin; Yu-Chi Lee; Hao-Min Liu; Herming Chiueh; Tai-Shih Chi; Chia-Hsiang Yang (IEEE Trans. Circuits Syst., 2020)

Design optimization for ADMM-Based SVM Training Processor for Edge Computing. - Shuo-An Huang; Yi-Yen Hsieh; Chia-Hsiang Yang (AICAS, 2021)

A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring. - Po-Shao Chen; Yen-Lung Chen; Yu-Chi Lee; Zih-Sing Fu; Chia-Hsiang Yang (A-SSCC, 2021)

A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices. - Sheng-Jung Yu; Yu-Chi Lee; Chia-Hsiang Yang (A-SSCC, 2021)

A Color Doppler Processing Engine with an Adaptive Clutter Filter for Portable Ultrasound Imaging Devices. - Yi-Lin Lo; Chia-Hsiang Yang (ICASSP, 2021)

4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images. - Hsueh-Yen Shen; Yu-Chi Lee; Tzu-Wei Tong; Chia-Hsiang Yang (ISSCC, 2021)

A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots. - Chieh Chung; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2021)

Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification. - Sung-Hao Wang; Yu-Kai Huang; Ching-Yuan Chen; Li-Yang Tang; Yen-Fu Tu; Po-Chih Chang; Chia-Fone Lee; Chia-Hsiang Yang; Chung-Chih Hung; Chien-Hao Liu; Ming-Dou Ker; Chung-Yu Wu (IEEE J. Solid State Circuits, 2021)

A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. - Yi-Chung Wu; Yen-Lung Chen; Chung-Hsuan Yang; Chao-Hsi Lee; Chao-Yang Yu; Nian-Shyang Chang; Ling-Chien Chen; Jia-Rong Chang; Chun-Pin Lin; Hung-Lieh Chen; Chi-Shi Chen; Jui-Hung Hung; et al. (IEEE J. Solid State Circuits, 2021)

A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome. - Yen-Lung Chen; Bo-Yi Chang; Chia-Hsiang Yang; Tzi-Dar Chiueh (IEEE Trans. Parallel Distributed Syst., 2021)

A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction. - Yi-Yen Hsieh; Yu-Cheng Lin; Chia-Hsiang Yang (ISSCC, 2022)

Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression. - Chen-Chien Kao; Yi-Yen Hsieh; Chao-Hung Chen; Chia-Hsiang Yang (MWSCAS, 2022)

A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training. - Zih-Sing Fu; Yu-Chi Lee; Alex Park 002; Chia-Hsiang Yang (VLSI Technology and Circuits, 2022)

A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality. - Wen-Cong Huang; I-Ting Lin; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (VLSI Technology and Circuits, 2022)

A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing. - Yu-Chen Lo; Yi-Chung Wu; Chia-Hsiang Yang (VLSI Technology and Circuits, 2022)

Hybrid Precoding Baseband Processor for 64 × 64 Millimeter Wave MIMO Systems. - Chen-Chien Kao; Chiao-En Chen; Chia-Hsiang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Achieving Accurate Automatic Sleep Apnea/Hypopnea Syndrome Assessment Using Nasal Pressure Signal. - Ying-Sheng Lin; Yi-Pao Wu; Yi-Chung Wu; Pei-Lin Lee; Chia-Hsiang Yang (IEEE J. Biomed. Health Informatics, 2022)

A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing. - Yen-Lung Chen; Chung-Hsuan Yang; Yi-Chung Wu; Chao-Hsi Lee; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Jui-Hung Hung; Chia-Hsiang Yang (ISSCC, 2023)

A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. - Cheng-Yan Du; Chieh-Fu Tsai; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (ISSCC, 2023)

A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots. - I-Ting Lin; Zih-Sing Fu; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (ISSCC, 2023)

A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing. - Liang-Hsin Lin; Zih-Sing Fu; Po-Shao Chen; Bo-Yin Yang; Chia-Hsiang Yang (VLSI Technology and Circuits, 2023)

A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing. - Yu-Cheng Lin; Chanmin Park; Wenda Zhao; Nan Sun 001; Youngcheol Chae; Chia-Hsiang Yang (VLSI Technology and Circuits, 2023)

A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices. - Yi-Lin Lo; Yu-Chen Lo; Chia-Hsiang Yang (VLSI Technology and Circuits, 2023)

A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for Seizure Prediction. - Yi-Yen Hsieh; Yu-Cheng Lin; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2023)

An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices. - Sheng-Jung Yu; Yu-Chi Lee; Liang-Hsin Lin; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2023)

A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator. - Hsueh-Yen Shen; Yu-Chi Lee; Tzu-Wei Tong; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2023)

An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping. - Chung-Hsuan Yang; Yi-Chung Wu; Yen-Lung Chen; Chao-Hsi Lee; Jui-Hung Hung; Chia-Hsiang Yang (IEEE Trans. Biomed. Circuits Syst., 2023)

An 8.1-to-353 TOPS/W Energy-Aware Deep-Learning Accelerator Supporting Dynamic Neural Networks. - Ting-Yang Chen; Yi-Lin Lo; Tun-Yu Chang; Chia-Hsiang Yang (A-SSCC, 2024)

A 28-nm 141.4TOPS/W Scalable Reconfigurable Deep Learning SoC for Large-Scale Neural Networks. - I-Hsuan Liu; I-Ting Lin; Yueh-Feng Tsai; Jeng-Sheng Hsieh; Vincent Chen; Chuei-Tang Wang; Chia-Hsiang Yang; Douglas C. H. Yu (A-SSCC, 2024)

30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization. - Yi-Chen Chu; Yu-Cheng Lin; Yu-Chen Lo; Chia-Hsiang Yang (ISSCC, 2024)

2.6 A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems. - Tang Lee; Ting-Yang Chen; I-Hsuan Liu; Chia-Hsiang Yang (ISSCC, 2024)

A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on Mobile Devices. - Chun-Wei Chang; I-Ting Lin; Chia-Hsiang Yang (VLSI Technology and Circuits, 2024)

A 99.2TOPS/W Transformer Learning Processor with Approximated Attention Score Gradient Computation and Ternary Vector-Based Speculation. - Ping-Sheng Wu; Yu-Cheng Lin; Chia-Hsiang Yang (VLSI Technology and Circuits, 2024)

A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring. - Po-Shao Chen; Yen-Lung Chen; Yu-Chi Lee; Zih-Sing Fu; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2024)

A 73.8k-Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition. - Tzu-Wei Tong; Tai-Jung Chen; Yi-Yen Hsieh; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2024)

A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems. - Yu-Cheng Lin; Ren-Hao Chiou; Chia-Hsiang Yang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality. - Wen-Cong Huang; I-Ting Lin; Ying-Sheng Lin; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2024)

A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices. - Yu-Hsuan Tsai; Yi-Cheng Lin; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Shi-Hao Chen; Chi-Shi Chen; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2024)

A 209TOPS/W Reinforcement Learning Processor with Full Speculation Exploitation and Inference-Training Parallel Processing. - Shih-Hao Chen; Ping-Sheng Wu; Brian Dean Soon; Chao-Hung Chen; Chun-Lung Hsu; Chih-Wei Liu; Chia-Hsiang Yang (CICC, 2025)

15.1 A 3.9mW 200words/min Neural Signal Processor in Speech Decoding for Brain-Machine Interface. - Tun-Yu Chang; Jeng-Bang Wang; Yu-Hsuan Tsai; Chia-Hsiang Yang (ISSCC, 2025)

2.8: A 210fps Image Signal Processor for 4K Ultra HD True Video Super Resolution. - Ying-Sheng Lin; Jun Nishimura; Chia-Hsiang Yang (ISSCC, 2025)

17.3 A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-Party Computation. - Liang-Hsin Lin; Yao-Kai Yang; Chia-Hsiang Yang (ISSCC, 2025)

Guest Editorial Introduction to the Special Section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC). - Wei-Zen Chen; Benton H. Calhoun; Chia-Hsiang Yang; Shreyas Sen; Jun Yang (IEEE J. Solid State Circuits, 2025)

A 40-nm 169mW Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices. - Yi-Lin Lo; Yu-Chen Lo; Chia-Hsiang Yang (IEEE Trans. Biomed. Circuits Syst., 2025)

A 44.3-mW 62.4-fps Hyperspectral Image Processor for Spectral Unmixing in MAV Remote Sensing. - Yu-Chen Lo; Yi-Chung Wu; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2025)

A 40-nm 131-mW 6.4-Gb/s 256 × 32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems. - Tang Lee; Ting-Yang Chen; I-Hsuan Liu; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2025)

A 28-nm 142-mW Motion-Control SoC for Autonomous Mobile Robots. - I-Ting Lin; Zih-Sing Fu; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2025)