A unified processor architecture for RISC & VLIW DSP. - Tay-Jyi Lin; Chie-Min Chao; Chia-Hsien Liu; Pi-Chen Hsiao; Shin-Kai Chen; Li-Chun Lin; Chih-Wei Liu; Chein-Wei Jen (ACM Great Lakes Symposium on VLSI, 2005)

Hierarchical instruction encoding for VLIW digital signal processors. - Chia-Hsien Liu; Tay-Jyi Lin; Chie-Min Chao; Pi-Chen Hsiao; Li-Chun Lin; Shin-Kai Chen; Chao-Wei Huang; Chih-Wei Liu; Chein-Wei Jen (ISCAS (4), 2005)