Lot streaming models with a limited number of capacitated transporters in multistage batch production systems. - Huan Neng Chiu; Jen-Huei Chang; Chia-Hsin Lee (Comput. Oper. Res., 2004)

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment. - Ding-Ming Kwai; Yung-Fa Chou; Meng-Fan Chang; Su-Meng Yang; Ding-Sheng Chen; Min-Chung Hsu; Yu-Zhen Liao; Shiao-Yi Lin; Yu-Ling Sung; Chia-Hsin Lee; Hsin-Kun Hsu (MTDT, 2006)

SRAM Cell Current in Low Leakage Design. - Ding-Ming Kwai; Ching-Hua Hsiao; Chung-Ping Kuo; Chi-Hsien Chuang; Min-Chung Hsu; Yi-Chun Chen; Yu-Ling Sung; Hsien-Yu Pan; Chia-Hsin Lee; Meng-Fan Chang; Yung-Fa Chou (MTDT, 2006)

Hierarchical power network synthesis for multiple power domain designs. - Chieh-Jui Lee; Shih-Ying Liu; Chuan-Chia Huang; Hung-Ming Chen; Chang-Tzu Lin; Chia-Hsin Lee (ISQED, 2012)

3-D centric technology and realization with TSV. - Chang-Tzu Lin; Chia-Hsin Lee; Tsu-Wei Tseng; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2012)

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. - Chi-Wen Pan; Yu-Min Lee; Pei-Yu Huang; Chi-Ping Yang; Chang-Tzu Lin; Chia-Hsin Lee; Yung-Fa Chou; Ding-Ming Kwai (ASP-DAC, 2013)

Effective power network prototyping via statistical-based clustering and sequential linear programming. - Shih-Ying Sean Liu; Chieh-Jui Lee; Chuan-Chia Huang; Hung-Ming Chen; Chang-Tzu Lin; Chia-Hsin Lee (DATE, 2013)

Enabling inter-die co-optimization in 3-D IC with TSVs. - Chang-Tzu Lin; Tsu-Wei Tseng; Yung-Fa Chou; Chia-Hsin Lee; Ding-Ming Kwai (VLSI-DAT, 2013)

Improving power delivery network design by practical methodologies. - Chia-Chi Huang; Chang-Tzu Lin; Wei-Syun Liao; Chieh-Jui Lee; Hung-Ming Chen; Chia-Hsin Lee; Ding-Ming Kwai (ICCD, 2014)

A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. - Tsu-Wei Tseng; Chang-Tzu Lin; Chia-Hsin Lee; Yung-Fa Chou; Ding-Ming Kwai (VLSI-DAT, 2014)

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. - Pei-Wen Luo; Chi-Kang Chen; Yu-Hui Sung; Wei Wu 024; Hsiu-Chuan Shih; Chia-Hsin Lee; Kuo-Hua Lee; Ming-Wei Li; Mei-Chiang Lung; Chun-Nan Lu; Yung-Fa Chou; Po-Lin Shih; et al. (VLSIC, 2015)

A New Methodology for Noise Sensor Placement Based on Association Rule Mining. - Yu-Hsiang Hung; Sheng-Hsin Fang; Hung-Ming Chen; Shen-Min Chen; Chang-Tzu Lin; Chia-Hsin Lee (ACM Great Lakes Symposium on VLSI, 2016)

Electroencephalography Connectivity Assesses Cognitive Disorders of Autistic Children During Game-Based Social Interaction. - Yi-Li Tseng; Hong-Hsiang Liu; Yen-Nan Chiu; Chia-Hsin Lee; Wen-Che Tsai; Yang-Min Lin; Yi-Ling Chien (IEEE Trans. Cogn. Dev. Syst., 2024)