A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS. - Yung-Hui Chung; Chia-Hui Tien; Qi-Feng Zeng (APCCAS, 2019)

A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes. - Yung-Hui Chung; Chia-Hui Tien; Qi-Feng Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 105-dB SFDR 16-bit SAR ADC with a Window Capacitor Calibration Scheme. - Qi-Fen Zeng; Chia-Hui Tien; Yung-Hui Chung (ISCAS, 2024)