Energy analysis of bipartition architecture for pipelined circuits. - Shanq-Jang Ruan; Edwin Naroska; Yen-Jen Chang; Chia-Lin Ho; Feipei Lai (APCCAS (2), 2002)

Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. - Shanq-Jang Ruan; Edwin Naroska; Chia-Lin Ho; Feipei Lai (ICCD, 2002)

A novel approach for digital waveform compression. - Edwin Naroska; Shanq-Jang Ruan; Chia-Lin Ho; Said Mchaalia; Feipei Lai; Uwe Schwiegelshohn (ASP-DAC, 2003)

Energy and area efficient hardware implementation of 4K Main-10 HEVC decoder in Ultra-HD Blu-ray player and TV systems. - Tsu-Ming Liu; Yung-Chang Chang; Chih-Ming Wang; Hue-Min Lin; Chia-Yun Cheng; Chun-Chia Chen; Min-Hao Chiu; Sheng-Jen Wang; Ping Chao; Meng-Jye Hu; Fu-Chun Yeh; Shun-Hsiang Chuang; et al. (ICME, 2015)

A 2.6mm2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications. - Chi-Cheng Ju; Tsu-Ming Liu; Yung-Chang Chang; Chih-Ming Wang; Chia-Yun Cheng; Hue-Min Lin; Chun-Chia Chen; Min-Hao Chiu; Ping Chao; Ming-Long Wu; Meng-Jye Hu; Sheng-Jen Wang; et al. (ESSCIRC, 2016)

New product identification and design through super-system trimming. - D. Daniel Sheu; Jealousy Hong; Chia-Lin Ho (Comput. Ind. Eng., 2017)