Mixed-VTH (MVT) CMOS circuit design for low power cell libraries. - Jiun-Yi Lin; Li-Rong Wang; Chia-Lin Hu; Shyh-Jye Jou (SoCC, 2007)

A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. - Li-Rong Wang; Yi-Wei Chiu; Chia-Lin Hu; Ming-Hsien Tu; Shyh-Jye Jou; Chung-Len Lee (ISCAS, 2008)

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. - Hung-Ming Chen; Chia-Lin Hu; Kang-Yu Chang; Alexandra Küster; Yu-Hsien Lin; Po-Shen Kuo; Wei-Tung Chao; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ICCAD, 2020)

A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. - Yu-Hsien Lin; Chi Liu; Chia-Lin Hu; Kang-Yu Chang; Jia-Yin Chen; Shyh-Jye Jou (VLSI-DAT, 2021)

On Optimizing Capacitor Array Design for Advanced Node SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Kang-Yu Chang; Mark Po-Hung Lin; Shyh-Jye Jou; Hung-Yu Chen; Chien-Nan Jimmy Liu; Hung-Ming Chen (SMACD, 2022)

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. - Chi Liu; Shao-Tzu Li; Tong-Lin Pan; Cheng-En Ni; Yun Sung; Chia-Lin Hu; Kang-Yu Chang; Tuo-Hung Hou; Tian-Sheuan Chang; Shyh-Jye Jou (VLSI-DAT, 2022)

On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Mark Po-Hung Lin; Yu-Szu Chung; Shyh-Jye Jou; Jieh-Tsorng Wu; Shiuh-Hua Wood Chiang; Chien-Nan Jimmy Liu; Hung-Ming Chen (ASP-DAC, 2023)