Efficient K-Means VLSI Architecture for Vector Quantization. - Hui-Ya Li; Wen-Jyi Hwang; Chih-Chieh Hsu; Chia-Lung Hung (SCIA, 2009)

Hardware Implementation of k-Winner-Take-All Neural Network with On-chip Learning. - Hui-Ya Li; Chien-Min Ou; Yi-Tsan Hung; Wen-Jyi Hwang; Chia-Lung Hung (CSE, 2010)

An Efficient Pipelined Architecture for Fast Competitive Learning. - Hui-Ya Li; Chia-Lung Hung; Wen-Jyi Hwang (ICA3PP (2), 2010)

Efficient pipelined architecture for competitive learning. - Hui-Ya Li; Chia-Lung Hung; Wen-Jyi Hwang; Yi-Tsan Hung (J. Parallel Distributed Comput., 2011)