Peak Power Minimization through Power Management Scheduling. - Shih-Hsu Huang; Chun-Hua Cheng; Chung-Hsin Chiang; Chia-Ming Chang 002 (APCCAS, 2006)

Fast multi-domain clock skew scheduling for peak current reduction. - Shih-Hsu Huang; Chia-Ming Chang 002; Yow-Tyng Nieh (ASP-DAC, 2006)

State re-encoding for peak current minimization. - Shih-Hsu Huang; Chia-Ming Chang 002; Yow-Tyng Nieh (ICCAD, 2006)

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. - Shih-Hsu Huang; Chun-Hua Cheng; Chung-Hsin Chiang; Chia-Ming Chang 002 (JCIS, 2006)

Clock Period Minimization with Minimum Delay Insertion. - Shih-Hsu Huang; Chun-Hua Cheng; Chia-Ming Chang 002; Yow-Tyng Nieh (DAC, 2007)

A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. - Shih-Hsu Huang; Chia-Ming Chang 002; Yow-Tyng Nieh (J. Inf. Sci. Eng., 2007)

Type-matching clock tree for zero skew clock gating. - Chia-Ming Chang 002; Shih-Hsu Huang; Yuan-Kai Ho; Jia-Zong Lin; Hsin-Po Wang 002; Yu-Sheng Lu (DAC, 2008)

Opposite-phase register switching for peak current minimization. - Shih-Hsu Huang; Chia-Ming Chang 002; Yow-Tyng Nieh (ACM Trans. Design Autom. Electr. Syst., 2009)

Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. - Shih-Hsu Huang; Chia-Ming Chang 002; Wen-Pin Tu; Song-Bin Pan (ASP-DAC, 2010)

Low-power anti-aging zero skew clock gating. - Shih-Hsu Huang; Wen-Pin Tu; Chia-Ming Chang 002; Song-Bin Pan (ACM Trans. Design Autom. Electr. Syst., 2013)