Transistor Level Synthesis for Static CMOS Combinational Circuits. - Chia-Pin R. Liu; Jacob A. Abraham (Great Lakes Symposium on VLSI, 1999)

Transistor-mapped binary decision diagram for CMOS circuits. - Chia-Pin R. Liu (CAINE, 2006)

Traffic Monitoring for a Network Visualization Environment. - Chia-Pin R. Liu; Shaofeng Yang; Mahmound A. Manzoul (CATA, 2006)

Gate Model Extraction from CMOS Transistor Circuits. - Chia-Pin R. Liu (CAINE, 2007)

A Novel Synthesis for Dynamic CMOS Circuits. - Chia-Pin R. Liu (CAINE, 2008)

Floorplan Optimization for Hierarchical VLSI Design. - Chia-Pin R. Liu (CAINE, 2009)

A Novel Floorplanning for Hierarchical VLSI Design. - Chia-Pin R. Liu (CATA, 2009)