An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. - Shen-Fu Hsiao; Ming-Yu Tsai; Ming-Chih Chen; Chia-Sheng Wen (ISCAS (3), 2005)

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. - Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen (APCCAS, 2006)

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. - Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen (ISCAS, 2008)

Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method. - Shen-Fu Hsiao; Chia-Sheng Wen; Kun-Chih Chen (APCCAS, 2010)

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. - Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system. - Shen-Fu Hsiao; Chi-Guang Lin; Po-Han Wu; Chia-Sheng Wen (APCCAS, 2012)

Low-cost designs of rectangular to polar coordinate converters for digital communication. - Shen-Fu Hsiao; Chia-Sheng Wen; Cheng-Han Lee; Andrew Lee (APCCAS, 2012)

Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions. - Shen-Fu Hsiao; Hou-Jen Ko; Chia-Sheng Wen (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units. - Shen-Fu Hsiao; Po-Han Wu; Chia-Sheng Wen; Li-Yao Chen (VLSI-DAT, 2013)

Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. - Shen-Fu Hsiao; Hou-Jen Ko; Yu-Ling Tseng; Wen-Liang Huang; Shin-Hung Lin; Chia-Sheng Wen (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Compression of Lookup Table for Piecewise Polynomial Function Evaluation. - Shen-Fu Hsiao; Chia-Sheng Wen; Po-Han Wu (DSD, 2014)

Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. - Shen-Fu Hsiao; Po-Han Wu; Chia-Sheng Wen; Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Hierarchical Multipartite Function Evaluation. - Shen-Fu Hsiao; Chia-Sheng Wen; Yi-Hau Chen; Kuei-Chun Huang (IEEE Trans. Computers, 2017)