A scalable DCO design for portable ADPLL designs. - Chia-Tsun Wu; Wei Wang 252; I-Chyn Wey; An-Yeu Wu (ISCAS (6), 2005)

A portable all-digital pulsewidth control loop for SOC applications. - Wei Wang 252; I-Chyn Wey; Chia-Tsun Wu; An-Yeu Wu (ISCAS, 2006)

A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. - Chia-Tsun Wu; Wei Wang 252; I-Chyn Wey; An-Yeu Wu (ISCAS, 2006)

A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm. - Chia-Tsun Wu; Wen-Chung Shen; Wei Wang 252; An-Yeu Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)