Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs. - Shu-Han Wei; Yu-Min Lee; Chia-Tung Ho; Chih-Ting Sun; Liang-Chia Cheng (VLSI-DAT, 2013)

Incremental transient simulation of power grid. - Chia-Tung Ho; Yu-Min Lee; Shu-Han Wei; Liang-Chia Cheng (ISPD, 2014)

InTraSim: Incremental Transient Simulation of Power Grids. - Yu-Min Lee; Chia-Tung Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop. - Chia-Tung Ho; Andrew B. Kahng (ICCAD, 2019)

A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. - Chung-Kuan Cheng; Chia-Tung Ho; Daeyeal Lee; Dongwon Park (ICCAD, 2020)

Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning. - Chung-Kuan Cheng; Chia-Tung Ho; Chester Holtz; Bill Lin 001 (SLIP, 2021)

SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes. - Daeyeal Lee; Dongwon Park; Chia-Tung Ho; Ilgweon Kang; Hayoung Kim; Sicun Gao; Bill Lin 001; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT. - Chung-Kuan Cheng; Chia-Tung Ho; Daeyeal Lee; Bill Lin 001; Dongwon Park (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. - Chung-Kuan Cheng; Chia-Tung Ho; Chester Holtz (ASP-DAC, 2022)

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform. - Chung-Kuan Cheng; Chia-Tung Ho; Daeyeal Lee; Bill Lin 001 (IEEE Access, 2022)

Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. - Chung-Kuan Cheng; Chia-Tung Ho; Chester Holtz; Daeyeal Lee; Bill Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Novel Computer Aided Design (CAD) Methodology for Emerging Technologies to Fight the Stagnation of Moore's Law - Chia-Tung Ho (2022)

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model. - Chia-Tung Ho; Alvin Ho; Matthew Fojtik; Minsoo Kim; Shang Wei; Yaguang Li; Brucek Khailany; Haoxing Ren (ISPD, 2023)

DGR: Differentiable Global Router. - Wei Li 159; Rongjian Liang; Anthony Agnesina; Haoyu Yang; Chia-Tung Ho; Anand Rajaram; Haoxing Ren (DAC, 2024)

Novel Transformer Model Based Clustering Method for Standard Cell Design Automation. - Chia-Tung Ho; Ajay Chandna; David Guan; Alvin Ho; Minsoo Kim; Yaguang Li; Haoxing Ren (ISPD, 2024)

ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis. - Rongjian Liang; Chia-Tung Ho; Anthony Agnesina; Wen-Hao Liu 001; Haoxing Ren (MLCAD, 2024)

Large Language Model (LLM) for Standard Cell Layout Design Optimization. - Chia-Tung Ho; Haoxing Ren (CoRR, 2024)

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool. - Chia-Tung Ho; Haoxing Ren; Brucek Khailany (AAAI, 2025)

ChipVQA: Benchmarking Visual Language Models for Chip Design. - Haoyu Yang; Qijing Huang 001; Nathaniel Ross Pinckney; Walker J. Turner; Wenfei Zhou; Yanqing Zhang 002; Chia-Tung Ho; Chen-Chia Chang; Haoxing Ren (DATE, 2025)

DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent. - Chen-Chia Chang; Chia-Tung Ho; Yaguang Li; Yiran Chen 001; Haoxing Ren (ISPD, 2025)

Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design. - Chia-Tung Ho; Jing Gong; Yunsheng Bai; Chenhui Deng; Haoxing Ren; Brucek Khailany (CoRR, 2025)

Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing Debugging with Timing Debug Relation Graph. - Jatin Nainani; Chia-Tung Ho; Anirudh Dhurka; Haoxing Ren (CoRR, 2025)

PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification. - Yujie Zhao; Zhijing Wu 010; Hejia Zhang; Zhongming Yu; Wentao Ni; Chia-Tung Ho; Haoxing Ren; Jishen Zhao (CoRR, 2025)

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification. - Nathaniel Ross Pinckney; Chenhui Deng; Chia-Tung Ho; Yun-Da Tsai; Mingjie Liu; Wenfei Zhou; Brucek Khailany; Haoxing Ren (CoRR, 2025)