Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture. - Yi-Jung Chen; Wen-Wei Chang; Chia-Yin Liu; Cheng-En Wu; Bo-Yuan Chen; Ming-Ying Tsai (IEEE Access, 2017)

Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories. - Chia-Yin Liu; Cheng-En Wu; Yi-Jung Chen (RACS, 2018)

Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation. - Chia-Yin Liu; Hasitha Muthumala Waidyasooriya; Masanori Hariyama (CANDAR, 2019)

Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. - Chia-Yin Liu; Yi-Jung Chen; Masanori Hariyama (SAC, 2020)

Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators. - Chia-Yin Liu; Hasitha Muthumala Waidyasooriya; Masanori Hariyama (J. Supercomput., 2022)

Intermittent-Aware Neural Network Pruning. - Chih-Chia Lin; Chia-Yin Liu; Chih-Hsuan Yen; Tei-Wei Kuo; Pi-Cheng Hsiu (DAC, 2023)