A 76-MHz BiCMOS programmable logic sequencer. - Chiakang Sung; Paul T. Sasaki; Raymond Leung; Yuet-Ming Chu; Khanh M. Le; George W. Conner; Richard H. Lane; J. L. De Jong; Ron Cline (IEEE J. Solid State Circuits, 1989)

Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process. - John Turner; Richard Cliff; W. Leong; Cameron McClintock; Ninh Ngo; Khai Nguyen; Chiakang Sung; Bonnie Wang; J. Watson (FPL, 1995)

A silicon efficient FLEX 6000 programmable logic architecture. - Chiakang Sung; Richard Cliff; Joseph Huang; Bonnie Wang; Khai Nguyen; Xtaobao Wang; Kerry Veenstra; Bruce Pedersen; John Turner (CICC, 1998)

Optimizations for a Highly Cost-Efficient Programmable Logic Architecture. - Kerry Veenstra; Bruce Pedersen; Jay Schleicher; Chiakang Sung (FPGA, 1998)

A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM. - Sammy Cheung; Kar Keng Chua; Boon Jin Ang; Thow Pang Chong; Wei Lian Goay; Wei Yee Koay; Sin Wo Kuan; Chooi Pei Lim; Jiunn Shyong Oon; Theam Thye See; Chiakang Sung; Kim Pin Tan; et al. (CICC, 2000)

A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface. - Jeffrey Tyhach; Bonnie Wang; Chiakang Sung; Joseph Huang; Khai Nguyen; Xiaobao Wang; Yan Chong; Philip Pan; Henry Kim; Gopinath Rangan; Tzung-Chin Chang; Johnson Tan (CICC, 2004)

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface. - Jeffrey Tyhach; Bonnie Wang; Chiakang Sung; Joseph Huang; Khai Nguyen; Xiaobao Wang; Yan Chong; Philip Pan; Henry Kim; Gopinath Rangan; Tzung-Chin Chang; Johnson Tan (IEEE J. Solid State Circuits, 2005)