Clock skew optimization considering complicated power modes. - Chiao-Ling Lung; Zi-Yi Zeng; Chung-Han Chou; Shih-Chieh Chang (DATE, 2010)

Fault-tolerant 3D clock network. - Chiao-Ling Lung; Yu-Shih Su; Shih-Hsiu Huang; Yiyu Shi 001; Shih-Chieh Chang (DAC, 2011)

Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization. - Chiao-Ling Lung; Yi-Lun Ho; Ding-Ming Kwai; Shih-Chieh Chang (DATE, 2011)

TSV fault-tolerant mechanisms with application to 3D clock networks. - Chiao-Ling Lung; Jui-Hung Chien; Yiyu Shi 001; Shih-Chieh Chang (ISOCC, 2011)

Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs. - Chiao-Ling Lung; Yu-Shih Su; Hsih-Hsiu Huang; Yiyu Shi 001; Shih-Chieh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization. - Cody Hao Yu; Chiao-Ling Lung; Yi-Lun Ho; Ruei-Siang Hsu; Ding-Ming Kwai; Shih-Chieh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability. - Hsuan-Ming Chou; Ming-Yi Hsiao; Yi-Chiao Chen; Keng-Hao Yang; Jean Tsao; Chiao-Ling Lung; Shih-Chieh Chang; Wen-Ben Jone; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2015)