A compact DSP core with static floating-point unit & its microcode generation. - Tay-Jyi Lin; Hung-Yueh Lin; Chie-Min Chao; Chih-Wei Liu; Chein-Wei Jen (ACM Great Lakes Symposium on VLSI, 2004)

Static floating-point unit with implicit exponent tracking for embedded DSP. - Hung-Yueh Lin; Tay-Jyi Lin; Chie-Min Chao; Yen-Chin Liao; Chih-Wei Liu; Chein-Wei Jen (ISCAS (2), 2004)

A unified processor architecture for RISC & VLIW DSP. - Tay-Jyi Lin; Chie-Min Chao; Chia-Hsien Liu; Pi-Chen Hsiao; Shin-Kai Chen; Li-Chun Lin; Chih-Wei Liu; Chein-Wei Jen (ACM Great Lakes Symposium on VLSI, 2005)

Hierarchical instruction encoding for VLIW digital signal processors. - Chia-Hsien Liu; Tay-Jyi Lin; Chie-Min Chao; Pi-Chen Hsiao; Li-Chun Lin; Shin-Kai Chen; Chao-Wei Huang; Chih-Wei Liu; Chein-Wei Jen (ISCAS (4), 2005)

A 52mW 1200MIPS compact DSP for multi-core media SoC. - Shih-Hao Ou; Tay-Jyi Lin; Chao-Wei Huang; Yu-Ting Kuo; Chie-Min Chao; Chih-Wei Liu; Chein-Wei Jen (ASP-DAC, 2006)

A Compact DSP Core with Static Floating-Point Arithmetic. - Tay-Jyi Lin; Hung-Yueh Lin; Chie-Min Chao; Chih-Wei Liu; Chih-Wei Jen (J. VLSI Signal Process., 2006)