7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell. - Chien-Chen Lin; Jui-Yu Hung; Wen-Zhang Lin; Chieh-Pu Lo; Yen-Ning Chiang; Hsiang-Jen Tsai; Geng-Hau Yang; Ya-Chin King; Chrong Jung Lin; Tien-Fu Chen; Meng-Fan Chang (ISSCC, 2016)

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. - Yongpan Liu; Zhibo Wang 004; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Chien-Chen Lin; Qi Wei 001; Yu Wang 002; Ya-Chin King; Chrong Jung Lin; Pedram Khalili; et al. (ISSCC, 2016)

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors. - Albert Lee; Chieh-Pu Lo; Chien-Chen Lin; Wei-Hao Chen; Kuo-Hsiang Hsu; Zhibo Wang 004; Fang Su; Zhe Yuan; Qi Wei 001; Ya-Chin King; Chrong Jung Lin; Hochul Lee; et al. (IEEE J. Solid State Circuits, 2017)

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed. - Zhibo Wang 004; Yongpan Liu; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Jinyang Li 002; Chien-Chen Lin; Wei-Hao Chen; Hsiao-Yun Chiu; Wei-En Lin; Ya-Chin King; et al. (IEEE J. Solid State Circuits, 2017)

A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation. - Chieh-Pu Lo; Wen-Zhang Lin; Wei-Yu Lin; Huan-Ting Lin; Tzu-Hsien Yang; Yen-Ning Chiang; Ya-Chin King; Chrong Jung Lin; Yu-Der Chih; Tsung-Yung Jonathon Chang; Meng-Fan Chang (IEEE J. Solid State Circuits, 2019)

13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference. - Yu-Der Chih; Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Chieh-Pu Lo; Meng-Chun Shih; Kuei-Hung Shen; Harry Chuang; Tsung-Yung Jonathan Chang (ISSCC, 2020)

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. - Yu-Der Chih; Po-Hao Lee; Hidehiro Fujiwara; Yi-Chun Shih; Chia-Fu Lee; Rawan Naous; Yu-Lin Chen; Chieh-Pu Lo; Cheng-Han Lu; Haruki Mori; Wei-Cheng Zhao; Dar Sun; et al. (ISSCC, 2021)

A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations. - Yen-Cheng Chiu; Chia-Sheng Yang; Shih-Hsih Teng; Hsiao-Yu Huang; Fu-Chun Chang; Yuan Wu 009; Yu-An Chien; Fang-Ling Hsieh; Chung-Yuan Li; Guan-Yi Lin; Po-Jung Chen; Tsen-Hsiang Pan; et al. (ISSCC, 2022)

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device. - Yen-Cheng Chiu; Tung-Cheng Chang; Chun-Ying Lee; Je-Min Hung; Kuang-Tang Chang; Cheng-Xin Xue; Ssu-Yen Wu; Hui-Yao Kao; Peng Chen; Hsiao-Yu Huang; Shih-Hsih Teng; Chieh-Pu Lo; et al. (IEEE J. Solid State Circuits, 2022)

A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity. - Po-Hao Lee; Chia-Fu Lee; Yi-Chun Shih; Hon-Jarn Lin; Yen-An Chang; Cheng-Han Lu; Yu-Lin Chen; Chieh-Pu Lo; Chung-Chieh Chen; Cheng-Hsiung Kuo; Tan-Li Chou; Chia-Yu Wang; et al. (ISSCC, 2023)

CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems. - Mengtian Yang; Yipeng Wang 017; Shanshan Xie; Chieh-Pu Lo; Meizhi Wang; Sirish Oruganti; Rishabh Sehgal; Jaydeep P. Kulkarni (CICC, 2024)

30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing. - Yipeng Wang 017; Mengtian Yang; Chieh-Pu Lo; Jaydeep P. Kulkarni (ISSCC, 2024)

Unconventional Computing Using Ising Accelerators. - Jaydeep P. Kulkarni; Siddhartha Raman Sundara Raman; Shanshan Xie; Chieh-Pu Lo (Computer, 2025)