A low power and high speed Viterbi decoder chip for WLAN applications. - Chien-Ching Lin; Chia-Cho Wu; Chen-Yi Lee (ESSCIRC, 2003)

A dual mode channel decoder for 3GPP2 mobile wireless communications. - Chien-Ching Lin; Yen-Hsu Shih; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2004)

Multi-level memory systems using error control codes. - Hsie-Chia Chang; Chien-Ching Lin; Tien-Yuan Hsiao; Jieh-Tsorng Wu; Ta-Hui Wang (ISCAS (2), 2004)

A power and area efficient multi-mode FEC processor. - Yi-Chen Tseng; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee (ISCAS (2), 2004)

A 3.33Gb/s (1200,720) low-density parity check code decoder. - Chien-Ching Lin; Kai-Li Lin; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2005)

Design of a power-reduction Viterbi decoder for WLAN applications. - Chien-Ching Lin; Yen-Hsu Shih; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications. - Lei-Fone Chen; Yuan Chen; Lu-Chung Chien; Ying-Hao Ma; Chia-Hao Lee; Yu-Wei Lin; Chien-Ching Lin; Hsuan-Yu Liu; Terng-Yin Hsu; Chen-Yi Lee (ISSCC, 2006)

A low power turbo/Viterbi decoder for 3GPP2 applications. - Chien-Ching Lin; Yen-Hsu Shih; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. - Cheng-Chi Wong; Cheng-Hao Tang; Ming-Wei Lai; Yan-Xiu Zheng; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee; Yu.-T. Su (CICC, 2007)

MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications. - Terng-Ren Hsu; Chien-Ching Lin; Terng-Yin Hsu; Chen-Yi Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Self-Compensation Technique for Simplified Belief-Propagation Algorithm. - Yen-Chin Liao; Chien-Ching Lin; Hsie-Chia Chang; Chih-Wei Liu (IEEE Trans. Signal Process., 2007)

Multi-mode message passing switch networks applied for QC-LDPC decoder. - Chih-Hao Liu; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee; Yarsun Hsua (ISCAS, 2008)

A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. - Hsie-Chia Chang; Chien-Ching Lin; Fu-Ke Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. - Chih-Hao Liu; Chien-Ching Lin; Shao-Wei Yen; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee; Yar-Sun Hsu; Shyh-Jye Jou (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. - Cheng-Chi Wong; Ming-Wei Lai; Chien-Ching Lin; Hsie-Chia Chang; Chen-Yi Lee (IEEE J. Solid State Circuits, 2010)