Efficient minimization algorithms for fixed polarity AND/XOR canonical networks. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (Great Lakes Symposium on VLSI, 1993)

Boolean Matching Using Generalized Reed-Muller Forms. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (DAC, 1994)

Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (ISCAS, 1994)

Multilevel Logic Synthesis for Arithmetic Functions. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (DAC, 1996)

Logic Synthesis for Testability. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (Great Lakes Symposium on VLSI, 1996)

Generalized Reed-Muller Forms as a Tool to Detect Symmetries. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (IEEE Trans. Computers, 1996)

Boolean Functions Classification via Fixed Polarity Reed-Muller Forms. - Chien-Chung Tsai; Malgorzata Marek-Sadowska (IEEE Trans. Computers, 1997)

A novel combinational testability analysis by considering signal correlation. - Shih-Chieh Chang; Shi-Sen Chang; Wen-Ben Jone; Chien-Chung Tsai (ITC, 1998)

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (Asian Test Symposium, 2001)

Effect of RTL coding style on testability. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherhee; Wu-Tung Cheng; Sudhakar M. Reddy (CICC, 2001)

On RTL scan design. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Dan Devries; Wu-Tung Cheng; Sudhakar M. Reddy (ITC, 2001)

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. - Yu Huang 005; Sudhakar M. Reddy; Wu-Tung Cheng; Paul Reuter; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan (ITC, 2002)

Constraint Driven Pin Mapping for Concurrent SOC Testing. - Yu Huang 005; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan; Yanping Zhang; Wu-Tung Cheng; Sudhakar M. Reddy (ASP-DAC/VLSI Design, 2002)

On Concurrent Test of Core-Based SOC Design. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (J. Electron. Test., 2002)

Synthesis of Scan Chains for Netlist Descriptions at RT-Level. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Wu-Tung Cheng; Sudhakar M. Reddy (J. Electron. Test., 2002)

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Sudhakar M. Reddy (ISQED, 2003)